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W83627SF winbond i/o
W83627SF data sheet revision history pages dates version version on web main contents 1 n.a. 2000/09/17 0.50 first published 2 all 2000/11/15 0.6 0 new composition 3 4 5 6 7 8 9 10 please note tha t all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully ind emnify winbond for any damages resulting from such improper use or sales.
W83627SF p r e l i m i n a r y publication release date: nov. 2000 - i - preliminary revis ion 0. 6 0 table of contents general description -------------------------------- -------------------------------- ------------------ 1 pin configuration fo r W83627SF -------------------------------- -------------------------------- 6 1. pin description -------------------------------- -------------------------------- -------------------------------- ------------------------- 7 1.1 lpc interface -------------------------------- -------------------------------- -------------------------------- -------------------------- 7 1.2 fdc interface -------------------------------- -------------------------------- -------------------------------- -------------------------- 8 1.3 multi - mode paral lel port -------------------------------- -------------------------------- -------------------------------- ---- 9 1.4 serial port inte rface -------------------------------- -------------------------------- -------------------------------- ------------ 13 1.5 kbc interface -------------------------------- -------------------------------- -------------------------------- -------------------------- 15 1.6 acpi interface -------------------------------- -------------------------------- -------------------------------- ------------------------- 1 5 1.7 game port & midi port -------------------------------- -------------------------------- -------------------------------- ------------ 16 1.8 general purpose i/o port -------------------------------- -------------------------------- -------------------------------- -------- 17 1.8.1 general purpose i/o port 1 (power source is vcc) -------------------------------- -------------------------------- -------- 17 1.8.2 general purpose i/o port 2 (power source is vcc) -------------------------------- -------------------------------- -------- 17 1.8.3 general pur pose i/o port 3 (power souce is vsb) -------------------------------- -------------------------------- -------- 18 1.9 smart card inter face and general pur pose i/o port 7 (po wered by vcc except scpsnt# which is pow ered by vsb) -------------------------------- -------------------------------- ------------------------------ 19 1.10 general purpose i/o port 4 (powered by gp4pwr) -------------------------------- -------------------------------- 20 1.11 general purpose i/o port 5, 6 (powe red by vcc) -------------------------------- -------------------------------- ---- 20 1.12 32khz crystal o scillator -------------------------------- -------------------------------- -------------------------------- ---- 21 1.13 power pins -------------------------------- -------------------------------- -------------------------------- ------------------------------ 21 2. lpc (low pin coun t) interface -------------------------------- -------------------------------- 22 3. fdc functional de scription -------------------------------- -------------------------------- -- 23 3.1 W83627SF fdc -------------------------------- -------------------------------- -------------------------------- ----------------------------- 23 3.1.1 at interface -------------------------------- -------------------------------- -------------------------------- --------------------------- 23 3.1.2 fifo (data) -------------------------------- -------------------------------- -------------------------------- -------------------------- 23 3.1.3 data separator -------------------------------- -------------------------------- -------------------------------- ---------------------- 24
W83627SF p r e l i m i n a r y publication release date: nov . 2000 - ii - revision 0. 6 0 3.1.4 write precompensation -------------------------------- -------------------------------- -------------------------------- ------------ 25 3.1.5 perpendicular recording mode -------------------------------- -------------------------------- -------------------------------- 25 3.1.6 fdc core -------------------------------- -------------------------------- -------------------------------- ----------------------------- 25 3.1.7 fdc commands -------------------------------- -------------------------------- -------------------------------- --------------------- 25 3.2 register descrip tions -------------------------------- -------------------------------- -------------------------------- ------------- 36 3.2.1 status register a (sa register) (read base address + 0) -------------------------------- ------------------------------- 36 3.2.2 status register b (sb register) (read base address + 1) -------------------------------- ------------------------------- 38 3.2.3 digital output register (do register) (write base address + 2) -------------------------------- --------------------- 40 3.2.4 tape drive register (td register) (read base address + 3) -------------------------------- --------------------------- 40 3.2.5 main status register (ms register) (read base address + 4) -------------------------------- ------------------------- 41 3.2.6 data rate register (dr register) (write base address + 4) -------------------------------- ---------------------------- 41 3.2.7 f ifo register (r/w base address + 5) -------------------------------- -------------------------------- ------------------------ 43 3.2.8 digital input register (di register) (read base address + 7) -------------------------------- ------------------------- 45 3.2.9 configuration control register (cc register) (write base address + 7) -------------------------------- ---------- 46 4. uart port -------------------------------- -------------------------------- -------------------------------- --- 47 4.1 universal asynch ronous receiver/tran smitter (uart a, uar t b) -------------------------------- ---- 47 4.2 register address -------------------------------- -------------------------------- -------------------------------- -------------------- 47 4.2.1 uart control register (ucr) (read/write) -------------------------------- -------------------------------- ---------------- 47 4.2.2 uart status register (usr) (read/write) -------------------------------- -------------------------------- ------------------ 50 4.2.3 handshake control register (hcr) (read/write) -------------------------------- -------------------------------- -------- 51 4.2.4 handshake status register (hsr) (read/write) -------------------------------- -------------------------------- ----------- 52 4.2.5 ua rt fifo control register (ufr) (write only) -------------------------------- -------------------------------- --------- 53 4.2.6 interrupt status register (isr) (read only) -------------------------------- -------------------------------- ----------------- 54 4.2.7 interrupt control register (icr) (read/write) -------------------------------- -------------------------------- ------------- 55 4.2.8 programmable baud generator (bll/bhl) (read/write) -------------------------------- ------------------------------ 55 4.2.9 user - defined register (udr) (read/write) -------------------------------- -------------------------------- ------------------ 56 5. cir receiver port -------------------------------- -------------------------------- --------------------- 57 5.1 cir registers -------------------------------- -------------------------------- -------------------------------- ---------------------------- 57 5.1.1 bank0.reg0 - receiver buffer registers (rbr) (read) -------------------------------- -------------------------------- --- 57 5.1.2 bank0.reg1 - interrupt control register (icr) -------------------------------- -------------------------------- ------------ 57 5.1.3 bank0.reg2 - interrupt status register (isr) -------------------------------- -------------------------------- --------------- 57 5.1.4 bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) --------------------- 58 5.1.5 bank0.reg4 - cir control register (ctr) -------------------------------- -------------------------------- ------------------ 58 5.1.6 bank0.reg5 - uart line status register (usr) -------------------------------- -------------------------------- ---------- 59 5.1.7 bank0.reg6 - remote infrared config register (rir_cfg) -------------------------------- ---------------------------- 60
W83627SF p r e l i m i n a r y publication release date: nov . 2000 - iii - revision 0. 6 0 5.1.8 bank0.reg7 - user defined register (udr/audr) -------------------------------- -------------------------------- ------- 61 5.1.9 bank1.reg0~1 - baud rate divisor latch (bll/bhl) -------------------------------- -------------------------------- --- 62 5.1.10 bank1.reg2 - version id regiister i (vid) -------------------------------- -------------------------------- ----------------- 63 5.1.11 bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) -------------------- 63 5.1.12 bank1.reg4 - timer low by te register (tmrl) -------------------------------- -------------------------------- ---------- 63 5.1.13 bank1.reg5 - timer high byte register (tmrh) -------------------------------- -------------------------------- -------- 63 6. parallel port -------------------------------- -------------------------------- -------------------------- 64 6.1 printer interfac e logic -------------------------------- -------------------------------- -------------------------------- --------- 64 6.2 enhanced paralle l port (epp) -------------------------------- -------------------------------- ------------------------------- 65 6.2.1 data swapper -------------------------------- -------------------------------- -------------------------------- ------------------------ 66 6.2.2 printer status buffer -------------------------------- -------------------------------- -------------------------------- ---------------- 66 6.2.3 printer control latch and printer control swapper -------------------------------- -------------------------------- ----- 67 6.2.4 epp address port -------------------------------- -------------------------------- -------------------------------- ------------------- 67 6.2.5 epp data port 0 - 3 -------------------------------- -------------------------------- -------------------------------- ------------------ 68 6.2.6 bit map of parallel port and epp registers -------------------------------- -------------------------------- ---------------- 68 6.2.7 epp pin descriptions -------------------------------- -------------------------------- -------------------------------- -------------- 69 6.2.8 epp operation -------------------------------- -------------------------------- -------------------------------- ----------------------- 69 6.3 extended capabil ities parallel (ecp) port -------------------------------- -------------------------------- ---------- 70 6.3.1 ecp register and mode definitions -------------------------------- -------------------------------- --------------------------- 70 6.3.2 data and ecpafifo port -------------------------------- -------------------------------- -------------------------------- ----------- 71 6.3.3 device status register (dsr) -------------------------------- -------------------------------- -------------------------------- ---- 71 6.3.4 device control register (dcr) -------------------------------- -------------------------------- -------------------------------- - 72 6.3.5 cfifo (parallel port data fifo) mode = 010 -------------------------------- -------------------------------- -------------- 73 6.3.6 ecpdfifo (ecp data fifo) mode = 011 -------------------------------- -------------------------------- -------------------- 73 6.3.7 tfifo (test fifo mode) mode = 110 -------------------------------- -------------------------------- -------------------------- 73 6.3.8 cnfga (configuration register a) mode = 111 -------------------------------- -------------------------------- ------------- 73 6.3.9 cnfgb (configuration register b) mode = 111 -------------------------------- -------------------------------- ------------- 73 6.3.10 ecr (extended control register) mode = all -------------------------------- -------------------------------- -------------- 74 6.3.11 bit map of ecp port registers -------------------------------- -------------------------------- -------------------------------- 75 6.3.12 ecp pin descriptions -------------------------------- -------------------------------- -------------------------------- ------------ 76 6.3.13 ecp operati on -------------------------------- -------------------------------- -------------------------------- --------------------- 77 6.3.14 fifo operation -------------------------------- -------------------------------- -------------------------------- -------------------- 77 6.3.15 dma transfers -------------------------------- -------------------------------- -------------------------------- --------------------- 78 6.3.16 programmed i/o (non - dma) mode -------------------------------- -------------------------------- ------------------------- 78 6.4 extension fdd mo de (extfdd) -------------------------------- -------------------------------- -------------------------------- 78
W83627SF p r e l i m i n a r y publication release date: nov . 2000 - iv - revision 0. 6 0 6.5 extension 2fdd m ode (ext2fdd) -------------------------------- -------------------------------- ----------------------------- 79 7. keyboard controll er -------------------------------- -------------------------------- ------------ 80 7.1 output buffer -------------------------------- -------------------------------- -------------------------------- ------------------------- 81 7.2 input buffer -------------------------------- -------------------------------- -------------------------------- ---------------------------- 81 7.3 status register -------------------------------- -------------------------------- -------------------------------- ---------------------- 81 7.4 commands -------------------------------- -------------------------------- -------------------------------- ------------------------------- 82 7.5 hardware gatea20 /keyboard reset cont rol logic -------------------------------- ---------------------------- 84 7.5.1 kb control register (logic device 5, cr - f0) -------------------------------- -------------------------------- -------------- 84 7.5.2 port 92 control register (default value = 0x24) -------------------------------- -------------------------------- --------- 84 8. general purpose i /o -------------------------------- -------------------------------- ----------------- 85 9. plug and play con figuration -------------------------------- -------------------------------- 89 9.1 compatible p np -------------------------------- -------------------------------- -------------------------------- ----------------------- 89 9.1.1 extended function registers -------------------------------- -------------------------------- -------------------------------- ---- 89 9.1.2 extended functions enable registers (efers) -------------------------------- -------------------------------- ------------ 90 9.1.3 extended function index registers (efirs), extended function data registers(efdrs) -------------------- 90 9.2 configuration se quence -------------------------------- -------------------------------- -------------------------------- -------- 90 9.2.1 enter the extended function mode -------------------------------- -------------------------------- ------------------------------ 90 9.2.2 configurate the configuration registers -------------------------------- -------------------------------- ---------------------- 91 9.2.3 exit the extended function mode -------------------------------- -------------------------------- -------------------------------- 91 9.2.4 software programming example -------------------------------- -------------------------------- -------------------------------- 91 10. acpi registers f eatures -------------------------------- -------------------------------- -------- 93 11. smart card inter face -------------------------------- -------------------------------- ----------- 94 11.1 receiver buffer register (rbr, read only at "base addre ss + 0" when bdlab = 0) ----------- 94 11.2 transmitter buf fer register (tbr, w rite only at "base a ddress + 0" when bd lab = 0) -- 94 11.3 interrupt contr ol register (icr, at "base address + 1" when bdlab = 0) ------------------------- 94 11.4 interrupt statu s register (isr, rea d only at "base addr ess + 2") -------------------------------- --- 95 11.5 smart card fifo control register (s cfr, write only at " base address + 2") ----------------- 96 11.6 smart card cont rol register (sccr, write only at "base address + 3") ------------------------- 97 11.7 interrupt enabl e register (ier, at "base address + 4") -------------------------------- ---------------------- 97 11.8 smart card st atus register (scsr, at "base address + 5") -------------------------------- --------------- 98 11.9 extended contro l register (ecr, at "base address + 7") -------------------------------- ------------------- 99
W83627SF p r e l i m i n a r y publication release date: nov . 2000 - v - revision 0. 6 0 11.10 baud rate divi sor latch high and b aud rate divisor lat ch low (bhl and bll at "base address + 1" and "base address + 0" respectively whe n bdlab = 1) ----------------------------- 100 12. serial irq -------------------------------- -------------------------------- -------------------------------- - 102 12.1 start frame -------------------------------- -------------------------------- -------------------------------- -------------------------- 102 12.2 irq/data frame -------------------------------- -------------------------------- -------------------------------- --------------------- 102 12.3 stop frame -------------------------------- -------------------------------- -------------------------------- ----------------------------- 103 13. configuration re gister -------------------------------- -------------------------------- ------- 104 13.1 chip (global) c ontrol register -------------------------------- -------------------------------- ---------------------------- 104 13.2 logical device 0 (fdc) -------------------------------- -------------------------------- -------------------------------- ------------ 110 13.3 logical device 1 (parallel port) -------------------------------- -------------------------------- -------------------------- 11 4 13.4 logica l device 2 (uart a) -------------------------------- -------------------------------- -------------------------------- ------ 115 13.5 logical device 3 (uart b) -------------------------------- -------------------------------- -------------------------------- ------- 115 13.6 logical device 5 (kbc) -------------------------------- -------------------------------- -------------------------------- ------------ 117 13.7 logical device 6 (cir) -------------------------------- -------------------------------- -------------------------------- ------------- 118 13.8 logical device 7 (game port and mi di port and gpio por t 1) -------------------------------- ------------- 119 13.9 logical device 8 (gpio port 2) -------------------------------- -------------------------------- -------------------------------- 120 13.10 logical device 9 (gpio port 3,4 ar e powered by standby source vsb) ------------------------------ 122 13.11 logical device a (acpi) -------------------------------- -------------------------------- -------------------------------- --------- 123 13.12 logical device b (smart card inter face) -------------------------------- -------------------------------- ---------- 131 13.13 logical device c (gpio port 5,6,7 this power of the po rts is source vcc) ------------------------- 1 31 14. specifications -------------------------------- -------------------------------- ------------------------- 1 34 14.1 absolute maximum ratings -------------------------------- -------------------------------- -------------------------------- 134 14.2 dc characterist ics -------------------------------- -------------------------------- -------------------------------- --------------- 134 15. application circ uits -------------------------------- -------------------------------- -------------- 137 15.1 parallel port e xtension fdd -------------------------------- -------------------------------- ------------------------------- 137 15.2 parallel port e xtension 2fdd -------------------------------- -------------------------------- ----------------------------- 138 15.3 four fdd mode -------------------------------- -------------------------------- -------------------------------- ----------------------- 1 38 16. ordering instruc tion -------------------------------- -------------------------------- ----------- 139 17. how to read the top marking -------------------------------- ----------------------------- 139 18. package dimensio ns -------------------------------- -------------------------------- --------------- 140
W83627SF preliminary publication release date: nov . 2000 - 1 - revision 0. 6 0 general description the W83627SF is the new generation of winbond's lpc i/o products. it features a whole new interface, namely lpc ( low pin count ) interface, which is supported in mainstream intel chip - set. this interface as its name suggests is to prov ide an economical implementation of i/o's interface with lower pin count and still maintains equivalent performance as its isa interface counterpart. approximately 40 pins are saved in lpc i/o comparing to isa implementation. with this additional freedom , we can implement more devices on a single chip as demonstrated in W83627SF's integration of game port and midi port. it is fully transparent in terms of software which means no bios or device driver update is needed except chip - specific configuration. as smart card application is gaining more and more attention, W83627SF also implements a smart card reader interface featuring smart wake - up function. this smart card reader interface fully meets the iso7816 and pc/sc (personal computer/smart card workgro up) standards. W83627SF provides a minimum external components and lowest cost soultion for smart card applications. the disk drive adapter functions of W83627SF include a floppy disk drive controller compatible with the industry standard 82077/765, data s eparator, write pre - compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and dma logic. the wide range of functions integrated onto the W83627SF greatly reduces the number of components req uired for interfacing with floppy disk drives. the W83627SF supports four 360k, 720k, 1.2m, 1.44m, or 2.88m disk drives and data transfer rates of 250 kb/s, 300 kb/s, 500 kb/s,1 mb/s, and 2 mb/s. the W83627SF provides two high - speed serial communication p orts (uarts), one of which supports serial infrared communication. each uart includes a 16 - byte send/receive fifo, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. both uarts provide legacy speed wi th baud rate up to 115.2k bps and also advanced speed with baud rates of 230k , 460k , or 921k bps which support higher speed modems. in addition, the W83627SF provides ir functions: irda 1.0 ( sir for 1.152k bps) and tv remote ir ( consumer ir , supporting nec , rc - 5, extended rc - 5, and recs - 80 protocols).
W83627SF preliminary publication release date: nov . 2000 - 2 - revision 0. 6 0 the W83627SF supports one pc - compatible printer port (spp), bi - directional printer port (bpp) and also enhanced parallel port (epp) and extended capabilities port (ecp). through the printer port interface pi ns, also available are: extension fdd mode and extension 2fdd mode allowing one or two external floppy disk drives to be connected. the configuration registers support mode selection, function enable/disable, and power down function selection. furthermore , the configurable pnp features are compatible with the plug - and - play feature demand of windows 95/98 tm , which makes system resource allocation more efficient than ever. the W83627SF provides functions that complies with acpi ( advanced configuration and po wer interface ), which includes support of legacy and acpi power management through pme# or psout# function pins. for onnow keyboard wake - up, onnow mouse wake - up, and onnow cir wake - up. the W83627SF also has auto power management to reduce the power consu mption. the keyboard controller is based on 8042 compatible instruction set with a 2k byte programmable rom and a 256 - byte ram bank. keyboard bios firmware are available with optional amikey tm - 2, phoenix multikey/42 tm , or customer code. the W83627SF prov ides a set of flexible i/o control functions to the system designer through a set of general purpose i/o ports. these gpio ports may serve as simple i/o or may be individually configured to provide a predefined alternate function. the W83627SF is made to fully comply with microsoft pc98 and pc99 hardware design guide . moreover, W83627SF is made to meet the specification of pc2000/pc2001's requirement in the power management: acpi and dpm (device power management). the W83627SF contains a game port and a mi di port. the game port is designed to support 2 joysticks and can be applied to all standard pc game control devices. they are very important for a entertainment or consumer computer.
W83627SF preliminary publication release date: nov . 2000 - 3 - revision 0. 6 0 features general meet lpc spec. 1.01 support ldrq#(lpc dma), serirq (serial irq) compliant with microsoft pc2000/pc2001 hardware design guide support dpm (device power management), acpi programmable configuration settings single 24 or 48 mhz clock input fdc compatible with ibm pc at disk drive systems variable write pre - compensation with track selectable capability support vertical recording format dma enable logic 16 - byte data fifos support floppy disk drives and tape drives detects all overrun and underrun conditions built - in address mark detection circuit to simplify t he read electronics fdd anti - virus functions with software write protect and fdd write enable signal (write data signal was forced to be inactive) support up to four 3.5 - inch or 5.25 - inch floppy disk drives completely compatible with industry standard 820 77 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate support 3 - mode fdd, and its win95/98 driver uart two high - speed 16550 compatible uarts with 16 - byte send/receive fifos midi compatible fully programmable serial - interf ace characteristics: --- 5, 6, 7 or 8 - bit characters --- even, odd or no parity bit generation/detection
W83627SF preliminary publication release date: nov . 2000 - 4 - revision 0. 6 0 --- 1, 1.5 or 2 stop bits generation internal diagnostic capabilities: --- loop - back controls for communicat ions link fault isolation --- break, parity, overrun, framing error simulation programmable baud generator allows division of 1.8461 mhz and 24 mhz by 1 to (2 16 - 1) maximum baud rate up to 921k bps for 14.769 mhz and 1.5m bps for 24 mhz infrare d support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps support sharp ask - ir protocol with maximum baud rate up to 57,600 bps support consumer ir parallel port compatible with ibm parallel port support ps/2 compatible bi - directiona l parallel port support enhanced parallel port (epp) - compatible with ieee 1284 specification support extended capabilities port (ecp) - compatible with ieee 1284 specification extension fdd mode s upports disk drive b; and extension 2fdd mode supports disk drives a and b through parallel port enhanced printer port back - drive current protection keyboard controller 8042 based with optional f/w from amikkey tm - 2, phoenix multikey/42 tm or customer code with 2k bytes of programmable rom, and 256 bytes of ram asynchronous access to two data registers and one status register software compatibility with the 8042 support ps/2 mouse support port 92 support both interrupt and polling modes fast gate a20 and ha rdware keyboard reset 8 bit timer/ counter support binary and bcd arithmetic
W83627SF preliminary publication release date: nov . 2000 - 5 - revision 0. 6 0 6 mhz, 8 mhz, 12 mhz, or 16 mhz operating frequency game port support two separate joysticks support every joystick two axis (x,y) and two button (a,b) controllers midi port th e baud rate is 31.25 kbaud 16 - byte input fifo 16 - byte output fifo general purpose i/o ports 40 programmable general purpose i/o ports general purpose i/o ports can serve as simple i/o ports, interrupt steering inputs, ,watching dog timer output, power le d output, infrared i/o pins, kbc control i/o pins, suspend led output, rsmrst# signal, pwrok signal, str(suspend to dram) function, vid control function, onnow functions keyboard wake - up by programmable keys mouse wake - up by programmable buttons cir wake - up by programmable keys smart card wake - up by scpsnt on now wake - up from all of the acpi sleeping states (s1 - s5) smart card reader interface pc/sc t=0, t=1 compliant iso7816 protocol compliant with 16 - byte send/receive fifos programmable baud generat or package 128 - pin pqfp
W83627SF preliminary publication release date: nov . 2000 - 6 - revision 0. 6 0 pin configuration fo r W83627SF 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 kdata kclk vsb kbrst a20gate kblock# ria# dcda# vss penkbc/souta sina pnpcsv#/dtra# hefras/rtsa# dsra# ctsa# vcc stb# afd# err# init# slin# pd0 pd1 pd2 pd3 40 39 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 susled/gp35 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 W83627SF scpwr/gp72/stgp72 scrst#/gp70/stgp70 s5in#/gp41 strctl/gp40 gp56/pvidlim1 gp55/vido4 gp54/vido3 gp53/vido2 gp52/vido1 gp51/vido0 gp50/pvidlim0 scpsnt/gp74 scio/gp73 vcc scclk/gp71 vss msi/gp20 mso/irqin0 gpsa2/gp17 gpsb2/gp16 gpy1/gp15 gpy2/p16/gp14 gpx2/p15/gp13 gpx1/p14/gp12 gpsb1/p13/gp11 gpsa1/p12/gp10 mclk mdata psout# psin cirrx#/gp34 rsmrst#/gp33 pwrok/gp32 pwrctl#/gp31 slp_sx#/gp30 vbat susclkin gp63 vcc ctsb# dsrb# rtsb#/engmto dtrb# sinb soutb/pen48 dcdb# rib# vss irtx/gp26 irrx/gp25 wdto/gp24 pled/gp23 gp22/vid14 gp21/vid13 xin vbat xout 32kout gp57clk/vidsel gp62/vidi2 gp61/vidi1 gp60/vidi0 gp4pwr gp42/stren pd4 pd5 pd6 pd7 ack# busy pe slct lreset# lframe# vcc3v lad0 lad1 lad2 lad3 serirq ldrq# pciclk vss pme# clkin dskchg# head# rdata# wp# trakd# vcc we# wd# step# dir# mob# dsa# dsb# moa# index# drvden1/irqin1/smi#/gp27 drvden0
W83627SF preliminary publication release date: nov . 2000 - 7 - revision 0. 6 0 1. pin description note: please refer to section 13.2 dc characteristics for details. i/o 8t - ttl level bi - directional pin with 8 ma source - sink capability i/o 12t - ttl level bi - direct ional pin with 12 ma source - sink capability i/o 12tp3 - 3.3v ttl level bi - directional pin with 12 ma source - sink capability i/od 12t - ttl level bi - directional pin open drain output with 12 ma sink capability i/od 16t - ttl level bi - directional pin open dr ain output with 16 ma sink capability i/od 24 - ttl level bi - directional pin open drain output with 24a sink capability out 2 - output pin with 2 ma source - sink capability out 12 - output pin with 12 ma source - sink capability o 12 tp3 - 3.3v output pin with 12 ma source - sink capability od 12 - open - drain output pin with 12 ma sink capability od 24 - open - drain output pin with 24 ma sink capability in cs - cmos level schmitt - trigger input pin in t - ttl level input pin in td - ttl level input pin with internal pull down resistor in ts - ttl level schmitt - trigger input pin in tsp3 - 3.3v ttl level schmitt - trigger input pin 1.1 lpc interface symbol pin i/o function clkin 18 in t system clock input. according to the input frequency 24mhz or 48mhz, it is selectable th rough register. default is 24mhz input. pme# 19 od 12 generated pme event. pciclk 21 in tsp3 pci clock input. ldrq# 22 o 12tp3 encoded dma request signal. serirq 23 i/od 12t serial irq input/output. lad[3:0] 24 - 27 i/o 12tp3 these signal lines communicat e address, control, and data information over the lpc bus between a host and a peripheral. lframe# 29 in tsp3 indicates start of a new cycle or termination of a broken cycle. lreset# 30 in tsp3 reset signal. it can connect to pcirst# signal on the host. s usclkin 75 in ts 32khz clock input , for cir only.
W83627SF preliminary publication release date: nov . 2000 - 8 - revision 0. 6 0 1.2 fdc interface symbol pin i/o function drvden0 1 od 24 drive density select bit 0. drvden1 smi# irqin1 gp27 2 od 12 od 12 in t i/od 12t drive density select bit 1. (default) system management interrupt. int errupt channel input. general purpose i/o port 2 bit 7. index# 3 in cs this schmitt - triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. this input pin is pulled up internally by a 1 k w resistor. the resistor can be disabled by bit 7 of l0 - crf0 (fipurdwn). moa# 4 od 24 motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. dsb# 5 od 24 drive select b. when set to 0, this pin enables disk driv e b. this is an open drain output. dsa# 6 od 24 drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. mob# 7 od 24 motor b on. when set to 0, this pin enables disk drive 1. this is an open drain output. dir# 8 od 24 direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion step# 9 od 24 step output pulses. this active low open drain output produces a pulse to move the head to another track. wd# 10 od 24 write data. this logic low open drain writes pre - compensation serial data to the selected fdd. an open drain output. we# 11 od 24 write enable. an open drain output. trak0# 13 in cs track 0. this schmitt - triggered input from the disk drive is active low when the he ad is positioned over the outermost track. this input pin is pulled up internally by a 1 k w resistor. the resistor can be disabled by bit 7 of l0 - crf0 (fipurdwn).
W83627SF preliminary publication release date: nov . 2000 - 9 - revision 0. 6 0 1.2 fdc interface, continued symbol pin i/o function wp# 14 in cs write protected. this active low schmitt input from the disk drive indicates that the diskette is write - protect ed. this input pin is pulled up internally by a 1 k w resistor. the resistor can be disabled by bit 7 of l0 - crf0 (fipurdwn). rdata# 15 in cs the read data input signal from the fdd. this input pin is pulled up internally by a 1 k w resistor. the resistor can be disabled by bit 7 of l0 - crf0 (fipurdwn). head# 16 od 24 head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 dskchg# 17 in cs diskette change. this signal is active low at power on and whenever the diskette is removed. this inp ut pin is pulled up internally by a 1 k resistor. the resistor can be disabled by bit 7 of l0 - crf0 (fipurdwn). 1.3 multi - mode parallel port symbol pin i/o function slct 31 in t printer mode: an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. od 12 extension fdd mode: we2# this pin is for extension fdd b; its function is the same as the we# pin of fdc. od 12 extension 2fdd mode: we2# this pin is for extension fdd a and b; its function is the same as the we# pin of fdc. pe 32 in t printer mode: an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. od 12 extension fdd mode: wd2# this pin is for extension fdd b; its function is the same as the wd# pin of fdc. od 12 extension 2fdd mode: wd2# this pin is for extension fdd a and b; its function is the same as the wd# pin of fdc.
W83627SF preliminary publication release date: nov . 2000 - 10 - revision 0. 6 0 1.3 multi - mode parallel port, continued symbol pin i/o function busy 33 in t printer mode: an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. od 12 extension fdd mode: mob2# this pin is for extension fdd b; its function is the same as the mob# pin of fdc. od 12 extension 2fdd mode: mob2# this pin is for extension fdd a and b; its function is the same as the mob# pin of fdc. ack# 34 in t od 12 od 12 printer mode: ack# an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the defini tion of this pin in ecp and epp mode. extension fdd mode: dsb2# this pin is for the extension fdd b; its functions is the same as the dsb# pin of fdc. extension 2fdd mode: dsb2# this pin is for extension fdd a and b; its function is the same as the dsb# p in of fdc. pd7 35 i/od 12t - od 12 printer mode: pd7 parallel port data bus bit 7. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri - state output. extension 2fdd mode : dsa2# this pin is for extension fdd a; its function is the same as the dsa# pin of fdc. pd6 36 i/od 12t - od 12 printer mode: pd6 parallel port data bus bit 6. refer to the description of the parallel port for the definition of this pin in ecp and e pp mode. extension fdd mode: this pin is a tri - state output. extension. 2fdd mode: moa2# this pin is for extension fdd a; its function is the same as the moa# pin of fdc. pd5 37 i/o 12t - - printer mode: pd5 parallel port data bus bit 5. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri - state output. extension 2fdd mode: this pin is a tri - state output.
W83627SF preliminary publication release date: nov . 2000 - 11 - revision 0. 6 0 1.3 multi - mode parallel port, continued symbol pin i/o functio n pd4 38 i/o 12t in t in t printer mode: pd4 parallel port data bus bit 4. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: dskchg2# this pin is for extension fdd b; the function of th is pin is the same as the dskchg# pin of fdc. it is pulled high internally. extension 2fdd mode: dskchg2# this pin is for extension fdd a and b; this function of this pin is the same as the dskchg# pin of fdc. it is pulled high internally. pd3 39 i/o 12 t in t in t printer mode: pd3 parallel port data bus bit 3. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: rdata2# this pin is for extension fdd b; its function is the same as the rd ata# pin of fdc. it is pulled high internally. extension 2fdd mode: rdata2# this pin is for extension fdd a and b; its function is the same as the rdata# pin of fdc. it is pulled high internally. pd2 40 i/o 12t in t in t printer mode: pd2 parallel port data bus bit 2. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: wp2# this pin is for extension fdd b; its function is the same as the wp# pin of fdc. it is pulled high internally. ex tension. 2fdd mode: wp2# this pin is for extension fdd a and b; its function is the same as the wp# pin of fdc. it is pulled high internally. pd1 41 i/o 12t in t in t printer mode: pd1 parallel port data bus bit 1. refer to the description of the para llel port for the definition of this pin in ecp and epp mode. extension fdd mode: trak02# this pin is for extension fdd b; its function is the same as the trak0# pin of fdc. it is pulled high internally. extension. 2fdd mode: trak02# this pin is for exten sion fdd a and b; its function is the same as the trak0# pin of fdc. it is pulled high internally.
W83627SF preliminary publication release date: nov . 2000 - 12 - revision 0. 6 0 1.3 multi - mode parallel port, continued symbol pin i/o function pd0 42 i/o 12t printer mode: pd0 parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. in t extension fdd mode: index2# this pin is for extension fdd b; its function is the same as the index# pin of fdc. it is pulled high internally. in t extension 2fdd mode: ind ex2# this pin is for extension fdd a and b; its function is the same as the index# pin of fdc. it is pulled high internally. slin# 43 od 12 od 12 od 12 printer mode: slin# output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: step2# this pin is for extension fdd b; its function is the same as the step# pin of fdc. extension 2fdd mode: step2# this pin is for extension fdd a and b; its function is the same as the step# pin of fdc. init# 44 od 12 od 12 od 12 printer mode: init# output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: dir2# this pin is for extension fdd b; its function is the same as the dir# pin of fdc. extension 2fdd mode: dir2# this pin is for extension fdd a and b; its function is the same as the dir# pin of fdc. err# 45 in t od 12 od 12 printer mode: err# a n active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: head2# this pin is for extension fdd b; its function is the same as the head#pin of fdc. extension 2fdd mode: head2# this pin is for extension fdd a and b; its function is the same as the head# pin of fdc.
W83627SF preliminary publication release date: nov . 2000 - 13 - revision 0. 6 0 1.3 multi - mode parallel port, continued symbol pin i/o function afd# 46 od 12 od 12 od 12 printer mode: afd# an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: drvden0 this p in is for extension fdd b; its function is the same as the drvden0 pin of fdc. extension 2fdd mode: drvden0 this pin is for extension fdd a and b; its function is the same as the drvden0 pin of fdc. stb# 47 od 12 printer mode: stb# an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. - extension fdd mode: this pin is a tri - state output. - extension 2fdd mode: this pin is a tri - state output. 1.4 serial port interface symbol pin i/o function ctsa# 49 in t clear to send. it is the modem control input. ctsb# 78 the function of these pins can be tested by reading bit 4 of the handshake status register. dsra# dsrb# 50 79 in t data set ready . an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. rtsa# 51 i/o 8t uart a request to send. an active low signal informs the modem or data set that the controller is ready to se nd data. hefras during power - on reset, this pin is pulled down internally and is defined as hefras, which provides the power - on value for cr26 bit 6 (hefras). a 4.7 k w is recommended if intends to pull up. (select 4eh as con figuration i/o port s address)
W83627SF preliminary publication release date: nov . 2000 - 14 - revision 0. 6 0 1.4 serial port interface, continued symbol pin i/o function rtsb# engmto 80 i/o 8t uart b request to send. an active low signal informs the modem or data set that the controller is ready to s end data. power on setting pin for enabling watch dog timer and its countdown. this pin is pulled down internally and provides the power - on value for bit 0 of cr30 and a count value of 0x0a for crf6 in logical device 8. a 4.7 k w is recommended if intends to pull up. dtra# pnpcsv# 52 i/o 8t uart a data terminal ready. an active low signal informs the modem or data set that the controller is ready to communicate. during power - on reset, this pin is pulled d own internally and is defined as pnpcsv# , which provides the power - on value for cr24 bit 0 ( pnpcsv# ). a 4.7 k w is recommended if intends to pull up. (clear the default value of fdc, uarts, prt, game port and midi port) dtrb# 8 1 i/o 8t uart b data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. sina sinb 53 82 in t serial input. it is used to receive serial data through the communication link. souta 54 i/o 8t uart a s erial output. it is used to transmit serial data out to the communication link. penkbc during power - on reset, this pin is pulled down internally and is defined as penkbc, which provides the power - on value for cr24 bit 2 (enkbc). a 4.7 k w resistor is recommended if intends to pull up. (enable kbc) soutb 83 i/o 8t uart b serial output. pen48 during power - on reset, this pin is pulled down internally and is defined as pen48, which provides the power - on value for cr24 bit 6 ( en48). a 4.7 k w resistor is recommended if intends to pull up. dcda# dcdb# 56 84 in t data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. ria# rib# 57 85 in t ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set.
W83627SF preliminary publication release date: nov . 2000 - 15 - revision 0. 6 0 1.5 kbc interface symbol pin i/o function kblock# 58 in t keyboard inhibit control input. this pin is after system reset. internal pull high. (kbc p17) a20ga te 59 out 12 gate a20 output. this pin is high after system reset. (kbc p21) kbrst 60 out 12 keyboard reset. this pin is high after system reset. (kbc p20) kclk 62 i/od 16t keyboard clock. kdata 63 i/od 16t keyboard data. mclk 65 i/od 16t ps2 mouse clock. mdata 66 i/od 16t ps2 mouse data. 1.6 acpi interface symbol pin i/o function psout# 67 od 12 panel switch output. this signal is used for wake - up system from s5 cold state. this pin is pulse output, active low. psin 68 i n td panel switch input. this pin is hig h active with an internal pull down resistor. vbat 74 pwr battery voltage input.
W83627SF preliminary publication release date: nov . 2000 - 16 - revision 0. 6 0 1.7 game port & midi port symbol pin i/o function msi 119 int midi serial data input. gp20 i/od 12t general purpose i/o port 2 bit 0. mso irqin0 120 out 12 in t midi serial data output. (default) alternate function input: interrupt channel input. gpsa2 121 incs active - low, joystick i switch input 2. this pin has an internal pull - up resistor. (default) gp17 i/od 12t general purpose i/o port 1 bit 7. gpsb2 122 incs active - low, joystick ii switch input 2. this pin has an internal pull - up resistor. (default) gp16 i/od 12 general purpose i/o port 1 bit 6. gpy1 123 i/od 12 joystick i timer pin. this pin connect to y positioning variable resistors for the josystick. (default) gp15 i/od 12t general purpose i/o port 1 bit 5. gpy2 gp14 p16 124 i/od 12 i/od 12t i/od 12t joystick ii timer pin. this pin connect to y positioning variable resistors for the josystick. (default) general purpose i/o port 1 bit 4. alternate function outp ut:kbc p16 i/o port. gpx2 gp13 p15 125 i/od 12 i/od 12t i/od 12t joystick ii timer pin. this pin connect to x positioning variable resistors for the josystick. (default) general purpose i/o port 1 bit 3. alternate function output:kbc p15 i/o port.
W83627SF preliminary publication release date: nov . 2000 - 17 - revision 0. 6 0 1.7 game port & midi port, continued symbol pin i/o function gpx1 gp12 p14 126 i/od 12 i/od 12t i/od 12t joystick i timer pin. this pin connect to x positioning variable resistors for the josystick. (default) general purpose i/o port 1 bit 2. alternate functio n output:kbc p14 i/o port. gpsb1 gp11 p13 127 incs i/od 12t i/od 12t active - low, joystick ii switch input 1. (default) general purpose i/o port 1 bit 1. alternate function output:kbc p13 i/o port. gpsa1 gp10 p12 128 incs i/od 12t i/od 12t active - low, joyst ick i switch input 1. (default) general purpose i/o port 1 bit 0. alternate function output:kbc p12 i/o port. 1.8 general purpose i/o port 1.8.1 general purpose i/o port 1 (power source is vcc) see 1.7 game port 1.8.2 general purpose i/o port 2 (power source is vcc) s ymbol pin i/o function gp26 irtx 87 i/od 12t out 12 general purpose i/o port 2 bit 6. alternate function output: infrared transmitter output. (default) gp25 irrx 88 i/od 12t in ts general purpose i/o port 2 bit 5. alternate function input: infrared receiver input. (default) gp24 wdto 89 i/od 12t od 12 general purpose i/o port 2 bit 4. watch dog timer output. (default) gp23 pled 90 i/od 24t od 24 general purpose i/o port 2 bit 3. power led output, this signal is low after system reset. (default) gp22 vidi4 91 i/od 12t in t general purpose i/o port 2 bit 2. alternate vid input bit 4. gp21 vidi3 92 i/od 12t in t general purpose i/o port 2 bit 1. alternate vid input bit 3.
W83627SF preliminary publication release date: nov . 2000 - 18 - revision 0. 6 0 1.8.3 general purpose i/o port 3 (power souce is vsb) symbol pin i/o function gp35 susled 64 i/od 24t od 24 general purpose i/o port 3 bit 5. suspend led output, it can program to flash when suspend state. this function can work without vcc. (default) gp34 cirrx# 69 i/od 12t od 12 general purpose i/o port 3 bit 4. consumer ir receiving input. this pin c an wake - up system from s5 cold. (default) gp33 rsmrst# 70 i/od 12t od 12 general purpose i/o port 3 bit 3. this pin generates the rsmrst signal while the vsb come in. (default) gp32 pwrok 71 i/od 12t od 12 general purpose i/o port 3 bit 2. this pin generat es the pwrok signal while the vcc come in. (default) gp31 pwrctl# 72 i/od 12t od 12 general purpose i/o port 3 bit 1. this pin generates the pwrctl# signal while the power failure. (default) gp30 slp_sx# 73 i/od 12t in t general purpose i/o port 3 bit 0. ch pset suspend c status input.
W83627SF preliminary publication release date: nov . 2000 - 19 - revision 0. 6 0 1.9 smart card interface and general purpose i/o port 7 (powered by vcc except scpsnt# which is powered by vsb) symbol pin i/o function scpsnt gp74 112 in ts i/o 12ts smart card present detection schmitt - trigger input. general purpose i/o port 7 bit 4. scio gp73 113 i/o 12t i/od 12t smart card data i/o channel. general purpose i/o port 7 bit 3. scpwr gp72 stgp72 115 out 12 i/o 12t smart card power control. general purpose i/o port 7 bit 2. power on setting pin for selecting funct ions of gp7. setting value is latched on the rising edge of powerok. this pin is internally pulled down during power on, a 4.7 k w resistor is recommended if intends to pull up. refer to detailed descrption of cr2c bit 6, 5. scclk gp71 116 out 12 i/o 12t smart card clock output. general purpose i/o port 7 bit 1. scrst# gp70 stgp70 118 out 12 i/o 12t smart card reset output. general purpose i/o port 7 bit 0. power on setting pin for selecting functions of gp7. setting value is l atched on the rising edge of powerok. this pin is internally pulled down during power on, a 4.7 k w resistor is recommended if intends to pull up. refer to detailed descrption of cr2c bit 6, 5.
W83627SF preliminary publication release date: nov . 2000 - 20 - revision 0. 6 0 1.10 general purpose i/o port 4 ( powered by gp4pwr) symbol pin i/o function gp4pwr 101 pwr +5v stand - by power supply dedicated for gp4. gp42 stren 102 i/o 12t general purpose i/o port 4 bit 2. power on setting pin for selecting functions of gp4. setting value is latched on the rising ed ge of rsmrst#. this pin is internally pulled down during power on, a 4.7 k w resistor is recommended if intends to pull up. refer to detailed descrption of cr29 bit 0. gp41 s5in# 103 i/o 12t general purpose i/o port 4 bit 1. s 5 input signal to indicate in s5 state. gp40 strctl 104 i/o 12t general purpose i/o port 4 bit 0. for suspend to ram function to control ram power. 1.11 general purpose i/o port 5, 6 (powered by vcc) symbol pin i/o function gp57 vidsel 97 i/o 12t general purp ose i/o port 5 bit 7. power on setting pin for selecting vid function. setting value is latched on the rising edge of powerok. this pin is internally pulled down during power on, a 4.7 k w resistor is recommended if intends to pull up. refer to detailed descrption of cr2c bit 7. gp56 pvidlim1 105 i/o 12t general purpose i/o port 5 bit 6. power on setting pin for selecting vid guarding function. setting value is latched on the rising edge of powerok. this pin is internally pu lled down during power on, a 4.7 k w resistor is recommended if intends to pull up. refer to detailed descrption of bit 6 of crfa in logical device c. gp55 vido4 106 i/od 12t od 12 general purpose i/o port 5 bit 5. alternate vid output bit 4. gp54 vido3 107 i/od 12t od 12 general purpose i/o port 5 bit 4. alternate vid output bit 3. gp53 vido2 108 i/od 12t od 12 general purpose i/o port 5 bit 3. alternate vid output bit 2.
W83627SF preliminary publication release date: nov . 2000 - 21 - revision 0. 6 0 1.11 general purpose i/o port 5, 6 (powered by vcc), con tinued symbol pin i/o function gp52 vido1 109 i/od 12t od 12 general purpose i/o port 5 bit 2. alternate vid output bit 1. gp51 vido0 110 i/od 12t od 12 general purpose i/o port 5 bit 1. alternate vid output bit 0. gp50 pvidlim0 111 i/o 12t general purpose i /o port 5 bit 0. power on setting pin for selecting vid guarding function. setting value is latched on the rising edge of powerok. this pin is internally pulled down during power on, a 4.7 k w resistor is recommended if intend s to pull up. refer to detailed descrption of bit 5 of crfa in logical device c. gp63 76 i/od 12t general purpose i/o port 6 bit 2. gp62 vidi2 98 i/od 12t in t general purpose i/o port 6 bit 2. alternate vid input bit 2. gp61 vidi1 99 i/od 12t in t general purpose i/o port 6 bit 1. alternate vid input bit 1. gp60 vidi0 100 i/od 12t in t general purpose i/o port 6 bit 0. alternate vid input bit 0. 1.12 32khz crystal oscillator symbol pin i/o function xin 93 in crystal input vbat 94 pwr dedicated power supply fo r oscillator. xout 95 out crystal output clk32kout 96 out 2 32khz output clock. 1.13 power pins symbol pin function vcc3v 28 +3.3v power supply for driving 3v on host interface. vcc 12, 48, 77, 114 +5v power supply for the digital circuitry. vsb 61 +5v s tand - by power supply for the digital circuitry. vss 20, 55, 86, 117 ground.
W83627SF preliminary publication release date: nov . 2000 - 22 - revision 0. 6 0 2. lpc (low pin count) interface lpc interface is to replace isa interface serving as a bus interface between host (chip - set) and peripheral (winbond i/o). data transfer on the lp c bus are serialized over a 4 bit bus. the general characteristics of the interface implemented in winbond lpc i/o are: one control line, namely lframe#, which is used by the host to start or stop transfers. no peripherals drive this signal. the lad[3:0] bus, which communicates information serially. the information conveyed are cycle type, cycle direction, chip select ion, address, data, and wait states. mr (master reset) of winbond isa i/o is replaced with a active low reset signal, namely lreset#, in winbond lpc i/o. an additional 33 mhz pci clock is needed in winbond lpc i/o for synchronization. dma requests ar e issued through ldrq#. interrupt requests are issued through serirq. power management events are issued through pme#. comparing to its isa counterpart, lpc implementation saves up to 40 pin counts (see table below) free for integrating more devices o n a single chip. winbond i/o interface pins count w83977ef d[7:0], sa[15:0], drq[3:0], dack#[3:0], tc, ior#, iow#, iochrdy, irqs 49 W83627SF lad[3:0], lframe#, pciclk, ldrq#, serirq, pme# 9 save 40 the transition from isa to lpc is transparent in te rms of software which means no bios or device driver update is needed except chip - specific configuration.
W83627SF preliminary publication release date: nov . 2000 - 23 - revision 0. 6 0 3. fdc functional descr iption 3.1 W83627SF fdc the floppy disk controller of the W83627SF integrates all of the logic required for floppy disk control. th e fdc implements a pc/at or ps/2 solution. all programmable options default to compatible values. the fifo provides better system performance in multi - master systems. the digital data separator supports up to 2 m bits/sec data rate. the fdc includes the following blocks: at interface, precompensation, data rate selection, digital data separator, fifo, and fdc core. 3.1.1 at interface the interface consists of the standard asynchronous signals: rd#, wr#, a0 - a3, irq, dma control, and a data bus. the address lin es select between the configuration registers, the fifo and control/status registers. this interface can be switched between pc/at, model 30, or ps/2 normal modes. the ps/2 register sets are a superset of the registers found in a pc/at. 3.1.2 fifo (data) the fi fo is 16 bytes in size and has programmable threshold values. all command parameter information and disk data transfers go through the fifo. data transfers are governed by the rqm and dio bits in the main status register. the fifo defaults to disabled mo de after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command. the advantage of the fifo is that it allows the system a larger dma latency without causing disk errors. the follo wing tables give several examples of the delays with a fifo. the data are based upon the following formula:
W83627SF preliminary publication release date: nov . 2000 - 24 - revision 0. 6 0 threshold # (1/data/rate) *8 - 1.5 m s = delay fifo threshold maximum delay to servicing a t 500k bps data rate 1 byte 1 16 m s - 1.5 m s = 14.5 m s 2 byte 2 16 m s - 1.5 m s = 30.5 m s 8 byte 8 16 m s - 1 .5 m s = 6.5 m s 15 byte 15 16 m s - 1.5 m s = 238.5 m s fifo threshold maximum delay to ser vicing at 1m bps data rate 1 byte 1 8 m s - 1.5 m s = 6.5 m s 2 byte 2 8 m s - 1.5 m s = 14.5 m s 8 byte 8 8 m s - 1.5 m s = 62.5 m s 15 byte 15 8 m s - 1.5 m s = 118.5 m s at the start of a command the fif o is always disabled and command parameters must be sent based upon the rqm and dio bit settings in the main status register. when the fdc enters the command execution phase, it clears the fifo of any data to ensure that invalid data are not transferred. an overrun and underrun will terminate the current command and the data transfer. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be ent ered. dma transfers are enabled with the specify command and are initiated by the fdc by activating the drq pin during a data transfer command. the fifo is enabled directly by asserting dack# and addresses need not be valid. note that if the dma controlle r is programmed to function in verify mode a pseudo read is performed by the fdc based only on dack#. this mode is only available when the fdc has been configured into byte mode (fifo disabled) and is programmed to do a read. with the fifo enabled the abov e operation is performed by using the new verify command. no dma operation is needed. ? @ 3.1.3 data separator the function of the data separator is to lock onto the incoming serial read data. when a lock is achieved the serial front end logi c of the chip is provided with a clock which is synchronized to the read data. the synchronized clock, called the data window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. serial t o parallel conversion logic separates the read data into clock and data bytes. the digital data separator (dds) has three parts: control logic, error adjustment, and speed tracking. the dds circuit cycles once every 12 clock cycles ideally. any data pulse input will be synchronized and then adjusted by immediate error adjustment. the control logic will generate rdd and rwd for every pulse input. during any cycle where no data pulse is present, the dds cycles are based on speed. a digital integrator is used to keep track of the speed changes in the input data stream.
W83627SF preliminary publication release date: nov . 2000 - 25 - revision 0. 6 0 3.1.4 write precompensation the write precompensation logic is used to minimize bit shifts in the rddata stream from the disk drive. shifting of bits is a known phenomenon in magnetic media and is dep endent on the disk media and the floppy drive. the fdc monitors the bit stream that is being sent to the drive. the data patterns that require precompensation are well known. depending upon the pattern, the bit is shifted either early or late relative to t he surrounding bits. 3.1.5 perpendicular recording mode the fdc is also capable of interfacing directly to perpendicular recording floppy drives. perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented ver tically. this scheme packs more data bits into the same area. fdcs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. some manufacturers offer drives that can read and write standard and perp endicular media in a perpendicular media drive. a single command puts the fdc into perpendicular mode. all other commands operate as they normally do. the perpendicular mode requires a 1 mbps data rate for the fdc. at this data rate the fifo eases the host interface bottleneck due to the speed of data transfer to or from the disk. 3.1.6 fdc core the W83627SF fdc is capable of performing twenty commands. each command is initiated by a multi - byte transfer from the microprocessor. the result can also be a multi - byt e transfer back to the microprocessor. each command consists of three phases: command, execution, and result. command the microprocessor issues all required information to the controller to perform a specific operation. execution the controller performs the specified operation. result after the operation is completed, status information and other housekeeping information is provided to the microprocessor. 3.1.7 fdc commands command symbol descriptions: c: cylinder number 0 - 256 d: data pattern dir: step d irection dir = 0, step out
W83627SF preliminary publication release date: nov . 2000 - 26 - revision 0. 6 0 dir = 1, step in ds0: disk drive select 0 ds1: disk drive select 1 dtl: data length ec: enable count eot: end of track efifo: enable fifo eis: enable implied seek eot: end of track fifothr: fifo threshol d gap: gap length selection gpl: gap length h: head number hds: head number select hlt: head load time hut: head unload time lock: lock efifo, fifothr, ptrtrk bits prevent affected by software reset mfm: mfm or fm mode mt: multitrack n: the num ber of data bytes written in a sector ncn: new cylinder number nd: non - dma mode ow: overwritten pcn: present cylinder number poll: polling disable pretrk: precompensation start track number r: record rcn: relative cylinder number r/w: read/write s c: sector/per cylinder sk: skip deleted data address mark srt: step rate time st0: status register 0 st1: status register 1 st2: status register 2 st3: status register 3 wg: write gate alters timing of we
W83627SF preliminary publication release date: nov . 2000 - 27 - revision 0. 6 0 (1) read data phase r/w d7 d6 d 5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ --------- ------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot -------------- --------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- ---- ---------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ -------- -------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
W83627SF preliminary publication release date: nov . 2000 - 28 - revision 0. 6 0 (2) read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior t o command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w - ------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st 2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n - ----------------------- sector id information after command execution
W83627SF preliminary publication release date: nov . 2000 - 29 - revision 0. 6 0 (3) read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ----------- ------------- ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system; fdd reads contents of all cylinders from index hole to eot result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ---- ------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------- ----------------- sector id information after command execution
W83627SF preliminary publication release date: nov . 2000 - 30 - revision 0. 6 0 (4) read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------- ------ -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r --------------------- --- ---------------------- n ------------------------ disk status after the command has been completed (5) verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w -------------- -------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- -------------------- dtl/sc ------------------- exec ution no data transfer takes place result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command executio n r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command executi on
W83627SF preliminary publication release date: nov . 2000 - 31 - revision 0. 6 0 (6) version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 e nhanced controller (7) write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n -------------- ---------- w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ----------------- ------- ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
W83627SF preliminary publication release date: nov . 2000 - 32 - revision 0. 6 0 (8) write deleted data phase r/w d7 d6 d5 d4 d3 d 2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------- ------------ h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w w -------------------- eot --------------- -------- -------------------- gpl ----------------------- -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------- ------ st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ------------------ ---- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
W83627SF preliminary publication release date: nov . 2000 - 33 - revision 0. 6 0 (9) format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- n ------------------------ --------------------- sc ----------------------- bytes/sector sectors/cylinder w w --------------------- gpl --------------------- ---------------------- d ------------------------ gap 3 filler byte execution for each sector repeat: w w w w ---------------------- c ------------------------ ---------------------- h ----- ------------------- ---------------------- r ------------------------ ---------------------- n ------------------------ input sector parameters result r r r -------------------- st0 ----------------------- -------------------- st1 -------------- --------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------- undefined ------------------- ---------------- undefined ------------------- ---------------- undefined ------------------- -- -------------- undefined ------------------- (10) recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt (11) sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command code result r r ---------------- st0 ------------------------- ---------------- pcn ------------------------- status information at the end of each seek operation
W83627SF preliminary publication release date: nov . 2000 - 34 - revision 0. 6 0 (12) specify phase r/w d7 d6 d5 d4 d3 d 2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w w | --------- srt ----------- | --------- hut ---------- | | ------------ hlt ---------------------------------- | nd (13) seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w w 0 0 0 0 0 hds ds1 ds0 -------------------- ncn ------------ ----------- execution r head positioned over proper cylinder on diskette (14) configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure in formation w w w 0 0 0 0 0 0 0 0 0 eis efifo poll | ------ fifothr ---- | | -------------------- pretrk ----------------------- | execution internal registers written (15) relative seek phase r /w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 command codes w w 0 0 0 0 0 hds ds1 ds0 | -------------------- rcn --------- ------------------- |
W83627SF preliminary publication release date: nov . 2000 - 35 - revision 0. 6 0 (16) dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 registers placed in fifo result r r r r r r r r r r -------- --------------- pcn - drive 0 -------------------- ----------------------- pcn - drive 1 ------------------- ----------------------- pcn - drive 2 -------------------- ----------------------- pcn - drive 3 ------------------- -------- srt ------------------ | --- ------ hut -------- ----------- hlt ----------------------------------- | nd ------------------------ sc/eot ---------------------- lock 0 d3 d2 d1 d0 gap wg 0 eis efifo poll | ------ fifothr -------- ----------------------- pretrk ------------------------- (17) perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d 0 gap wg (18) lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0 (19) sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------- st3 ------------------------- status information about disk d rive (20) invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w ------------- invalid codes ----------------- invalid codes (no operation - fdc goes to standby state) result r -------------------- st0 ---------------------- st0 = 80h
W83627SF preliminary publication release date: nov . 2000 - 36 - revision 0. 6 0 3.2 register descriptions there are several status, data, and control registers in W83627SF. these registers are defined below: address register of fset read write base address + 0 base address + 1 base address + 2 base address + 3 sa register sb register td register do register td register base address + 4 ms register dr register base address + 5 dt (fifo) register dt (fifo) register base a ddress + 7 di register cc register 3.2.1 status register a (sa register) (read base address + 0) this register is used to monitor several disk interface pins in ps/2 and model 30 modes. in ps/2 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 wp index head trak0 step drv2 init pending dir init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. drv2# (bit 6): 0 a second drive has been installed 1 a second drive has not been installed step (bit 5): this bit indicates the com plement of step# output. trak0# (bit 4): this bit indicates the value of trak0# input.
W83627SF preliminary publication release date: nov . 2000 - 37 - revision 0. 6 0 head (bit 3): this bit indicates the complement of head# output. 0 side 0 1 side 1 index# (bit 2): this bit indicates the value of index# output. wp# (bit 1): 0 d isk is write - protected 1 disk is not write - protected dir (bit 0) this bit indicates the direction of head movement. 0 outward direction 1 inward direction in ps/2 model 30 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 wp index head trak0 step f/f drq init pending dir init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. drq (bit 6): this bit indicates the value of drq output pin. step f/f (bit 5): this bit indicates the complement of latched step# output. trak0 (bit 4): this bit indicates the complement of trak0# input.
W83627SF preliminary publication release date: nov . 2000 - 38 - revision 0. 6 0 head# (bit 3): this bit indicates the value of head# output. 0 side 1 1 side 0 index (bit 2): this bit indicates the complement of index# output. wp (bit 1): 0 disk is not write - protected 1 disk is w rite - protected dir# (bit 0) this bit indicates the direction of head movement. 0 inward direction 1 outward direction 3.2.2 status register b (sb register) (read base address + 1) this register is used to monitor several disk interface pins in ps/2 and model 3 0 modes. in ps/2 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 mot en a we rdata toggle wdata toggle drive sel0 mot en b 1 1 drive sel0 (bit 5): this bit indicates the status of do register bit 0 (drive select bit 0). wdata toggle (bit 4): this bit changes state at every rising edge of the wd# output pin. rdata toggle (bit 3): this bit changes state at every rising edge of the rdata# output pin. we (bit 2): this bit indicates the complement of the we# output pin.
W83627SF preliminary publication release date: nov . 2000 - 39 - revision 0. 6 0 mot en b (bit 1) this bit indicates the complement of the mob# output pin. mot en a (bit 0) this bit indicates the complement of the moa# output pin. in ps/2 model 30 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 dsc dsd we f/f rdata f/f dsa dsb drv2 wd f/f drv2# (bit 7): 0 a second drive has been installed 1 a second drive has not been installed dsb# (bit 6): this bit indicates the status of dsb# output pin. dsa# (bit 5): this bit indicates the status of dsa# output pin. wd f/f(bit 4): this bit indicates the complement of the l atched wd# output pin at every rising edge of the wd# output pin. rdata f/f(bit 3): this bit indicates the complement of the latched rdata# output pin . we f/f (bit 2): this bit indicates the complement of latched we# output pin. dsd# (bit 1): 0 drive d has been selected 1 drive d has not been selected dsc# (bit 0): 0 drive c has been selected 1 drive c has not been selected
W83627SF preliminary publication release date: nov . 2000 - 40 - revision 0. 6 0 3.2.3 digital output register (do register) (write base address + 2) the digital output register is a write - only register controlling drive motors, drive selection, drq/irq enable, and fdc resetting. all the bits in this register are cleared by the mr pin. the bit definitions are as follows: 7 6 5 4 3 2 1-0 drive select: 00 select drive a 01 select drive b 10 select drive c 11 select drive d floppy disk controller reset active low resets fdc dma and int enable active high enable drq/irq motor enable a. motor a on when active high motor enable b. motor b on when active high motor enable c. motor c on when active high motor enable d. motor d on when active high 3.2.4 tape drive register (td register) (re ad base address + 3) this register is used to assign a particular drive number to the tape drive support mode of the data separator. this register also holds the media id, drive type, and floppy boot drive information of the floppy disk drive. in normal fl oppy mode, this register includes only bit 0 and 1. the bit definitions are as follows: 1 2 3 4 5 6 7 0 tape sel 0 tape sel 1 x x x x x x if three mode fdd function is enabled (en3mode = 1 in cr9), the bit definitions are as follows: 1 2 3 4 5 6 7 0 floppy boot drive 0 floppy boot drive 1 drive type id0 drive type id1 media id0 media id1 tape sel 0 tape sel 1
W83627SF preliminary publication release date: nov . 2000 - 41 - revision 0. 6 0 media id1 media id0 (bit 7, 6): these two bits are read only. these two bits reflect the value of cr8 bit 3, 2. drive type id1 drive type id0 (bit 5, 4): these two bits reflect two of the bits of cr7. which two bits are reflected depends on the last drive selected in the do register. floppy boot drive 1, 0 (bit 3, 2): these two bits reflect the value of cr8 bit 1, 0. tape sel 1, tape sel 0 (bit 1, 0): these two bits assign a logical drive number to the tape drive. drive 0 is n ot available as a tape drive and is reserved as the floppy disk boot drive. tape sel 1 tape sel 0 drive selected 0 0 none 0 1 1 1 0 2 1 1 3 3.2.5 main status register (ms register) (read base address + 4) the main status register is used to control the fl ow of data between the microprocessor and the controller. the bit definitions for this register are as follows: fdd 0 busy, (d0b = 1), fdd number 0 is in the seek mode. fdd 1 busy, (d1b = 1), fdd number 1 is in the seek mode. fdc busy, (cb). a read or write command is in the process when cb = high. non-dma mode, the fdc is in the non-dma mode, this bit is set only during the execution phase in non-dma mode. transition to low state indicates execution phase has ended. data input/output, (dio). if dio= high then transfer is from data register to the processor. if dio = low then transfer is from processor to data register. request for master (rqm). a high on this bit indicates data register is ready to send or receive data to or from the processor. 7 6 5 4 3 2 1 0 fdd 2 busy, (d2b = 1), fdd number 2 is in the seek mode. fdd 3 busy, (d3b = 1), fdd number 3 is in the seek mode. 3.2.6 data rate register (dr register) (write base address + 4) the data rate register is used to set the transfer r ate and write precompensation. the data rate of the fdc is programmed by the cc register for pc - at and ps/2 model 30 and ps/2 mode, and not by the dr register. the real data rate is determined by the most recent write to either of the dr register or cc reg ister.
W83627SF preliminary publication release date: nov . 2000 - 42 - revision 0. 6 0 1 2 3 4 5 6 7 0 drate0 drate1 precomp0 precomp1 precomp2 power down s/w reset 0 s/w reset (bit 7): this bit is the software reset bit. power - down (bit 6): 0 fdc in normal mode 1 fdc in power - down mode precomp2 precomp1 precomp0 (bit 4, 3, 2): these three bits select the valu e of write precompensation. the following tables show the precompensation values for the combination of these bits. precomp precompensation delay 2 1 0 250k - 1 mbps 2 mbps tape drive 0 0 0 default delays default delays 0 0 1 41. 67 ns 20.8 ns 0 1 0 83.34 ns 41.17 ns 0 1 1 125.00 ns 62.5ns 1 0 0 166.67 ns 83.3 ns 1 0 1 208.33 ns 104.2 ns 1 1 0 250.00 ns 125.00 ns 1 1 1 0.00 ns (disabled) 0.00 ns (disabled) data rate default preco mpensation delays 250 kb/s 125 ns 300 kb/s 125 ns 500 kb/s 125 ns 1 mb/s 41.67ns 2 mb/s 20.8 ns
W83627SF preliminary publication release date: nov . 2000 - 43 - revision 0. 6 0 drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc and reduced write current control. 00 500 kb/s (mfm), 250 kb/s (fm), rwc = 1 01 300 kb/s (mfm), 150 kb/s (fm), rwc = 0 10 250 kb/s (mfm), 125 kb/s (fm), rwc = 0 11 1 mb/s (mfm), illegal (fm), rwc = 1 the 2 mb/s data rate for tape drive is only support ed by setting 01 to drate1 and drate0 bits, as well as setting 10 to drt1 and drt0 bits which are two of the configure register crf4 or crf5 bits in logic device 0. please refer to the function description of crf4 or crf5 and data rate table for individual data rates setting. 3.2.7 fifo register (r/w base address + 5) the data register consists of four status registers in a stack with only one register presented to the data bus at a time. this register stores data, commands, and parameters and provides diskette - drive status information. data bytes are passed through the data register to program or obtain results after a command. in the W83627SF, this register defaults to fifo disabled mode after reset. the fifo can change its value and enable its operation throug h the configure command. status register 0 (st0) 7-6 5 4 3 2 1-0 us1, us0 drive select: 00 drive a selected 01 drive b selected 10 drive c selected 11 drive d selected hd head address: 1 head selected 0 head selected nr not ready: 1 drive is not ready 0 drive is ready ec equipment check: 1 when a fault signal is received from the fdd or the track 0 signal fails to occur after 77 step pulses 0 no error se seek end: 1 seek end 0 seek error ic interrupt code: 00 normal termination of command 01 abnormal termination of command 10 invalid command issue 11 abnormal termination because the ready signal from fdd changed state during command execution
W83627SF preliminary publication release date: nov . 2000 - 44 - revision 0. 6 0 status register 1 (st1) missing address mark. 1 when the fdc cannot detect the data address mark or the data address mark has been deleted. nw (not writable). 1 if a write protect signal is detected from the diskette drive during execution of write data. nd (no data). 1 if specified sector cannot be found during execution of a read, write or verifly data. not used. this bit is always 0. or (over rum). 1 if the fdc is not serviced by the host system within a certain time interval during data transfer. de (data error).1 when the fdc detects a crc error in either the id field or the data field. not used. this bit is always 0. en (end of track). 1 when the fdc tries to access a sector beyond the final sector of a cylinder. 0 1 2 3 4 5 6 7 status register 2 (st2) 1 2 3 4 5 6 7 0 bc (bad cylinder) md (missing address mark in data field). 1 if the fdc cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 no error 1 bad cylinder 0 no error sn (scan not satisfied) 1 during execution of the scan command 0 no error sh (scan equal hit) 1 during execution of the scan command, if the equal condition is satisfied 0 no error wc (wrong cylinder) 1 indicates wrong cylinder dd (data error in the data field) 1 if the fdc detects a crc error in the data field 0 no error cm (control mark) 1 during execution of the read data or scan command 0 no error not used. this bit is always 0 status register 3 (st3) 1 2 3 4 5 6 7 0 us0 unit select 0 us1 unit select 1 hd head address ts two-side to track 0 ry ready wp write protected ft fault
W83627SF preliminary publication release date: nov . 2000 - 45 - revision 0. 6 0 3.2.8 digital input register (di register) (read base address + 7) the digital input register is an 8 - bit read - only register used for diagnostic purposes. in a pc/xt or at only bit 7 is checked by the bios. when the register is read, bit 7 shows the complem ent of dskchg# , while other bits of the data bus remain in tri - state. bit definitions are as follows: x x x x x x x x 0 1 2 3 4 5 6 7 reserved for the hard disk controller during a read of this register, these bits are in tri-state dskchg in the ps/2 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 high dens drate0 drate1 dskchg 1 1 1 1 dskchg (bit 7): this bit indica tes the complement of the dskchg# input. bit 6 - 3: these bits are always a logic 1 during a read. drate1 drate0 (bit 2, 1): these two bits select the data rate of the fdc. refer to the dr register bits 1 and 0 for the settings corresponding to the indivi dual data rates. high dens# (bit 0): 0 500 kb/s or 1 mb/s data rate (high density fdd) 1 250 kb/s or 300 kb/s data rate in the ps/2 model 30 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 drate0 drate1 dskchg noprec dmaen 0 0 0
W83627SF preliminary publication release date: nov . 2000 - 46 - revision 0. 6 0 dskchg (bit 7): th is bit indicates the status of dskchg# input. bit 6 - 4: these bits are always a logic 1 during a read. dmaen (bit 3): this bit indicates the value of do register bit 3. noprec (bit 2): this bit indicates the value of cc register noprec bit. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. 3.2.9 configuration control register (cc register) (write base address + 7) this register is used to control the data rate. in the pc/at and ps/2 mode, the bit definitions are as follows: x x x x x x drate0 drate1 0 1 2 3 4 5 7 6 x: reserved bit 7 - 2: reserved. these bits should be set to 0. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. in the ps/2 model 30 mode, the bit definitio ns are as follows: 1 2 3 4 5 6 7 0 drate0 drate1 noprec x x x x x x : reserved bit 7 - 3: reserved. these bits should be set to 0. noprec (bit 2): this bit indicates no precompensation. it has no function and can be set by software. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc.
W83627SF preliminary publication release date: nov . 2000 - 47 - revision 0. 6 0 4. uart port 4.1 universal asynchronous receiver/transmitter (uart a, uart b) the uarts are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. the serial format, in order of tran smission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five - bit format only) or two stop bits. the uarts are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uarts also support the midi data rate. furthermore, the uarts also include complete modem control capability and a processor int errupt system that may be software trailed to the computing time required to handle the communication link. the uarts have a fifo mode to reduce the number of interrupts presented to the cpu. in each uart, there are 16 - byte fifos for both receive and transmit mode. 4.2 register address 4.2.1 uart control register (ucr) (read/write) the uart control register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection. 1 2 3 4 5 6 7 0 data length select bit 0 (dls0) data length select bit 1(dls1) multiple stop bits enable (msbe) parity bit enable (pbe) even parity enable (epe) parity bit fixed enable (pbfe) set silence enable (sse) baudrate divisor latch access bit (bdlab) bit 7: bdlab. w hen this bit is set to a logical 1, designers can access the divisor (in 16 - bit binary format) from the divisor latches of the baudrate generator during a read or write operation. when this bit is reset, the receiver buffer register, the transmitter buffer register, or the interrupt control register can be accessed. bit 6: sse. a logical 1 forces the serial output (sout) to a silent state (a logical 0). only irtx is affected by this bit; the transmitter is not affected. bit 5: pbfe. when pbe and pbfe of ucr are both set to a logical 1, (1) if epe is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if epe is logical 0, the parity bit is fixed as logical 1 to transmit and check.
W83627SF preliminary publication release date: nov . 2000 - 48 - revision 0. 6 0 table 4 - 1 uart register bit map b it n umber r egister a ddress b ase 0 1 2 3 4 5 6 7 + 0 bdlab = 0 r eceiver b uffer r egister (read only) rbr rx data bit 0 rx data bit 1 rx data bit 2 rx data bit 3 rx data bit 4 rx data bit 5 rx data bit 6 rx data bit 7 + 0 bdlab = 0 t r ansmitter b uffer r egister ( write only) tbr tx data bit 0 tx data bit 1 tx data bit 2 tx data bit 3 tx data bit 4 tx data bit 5 tx data bit 6 tx data bit 7 + 1 bdlab = 0 i nterrupt c ontrol r egister icr rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) usr interrupt enable (eusri) hsr interrupt enable (ehsri) 0 0 0 0 + 2 i nterrupt s tatus r egister ( read only ) isr "0" if interrupt pending interrupt status bit (0) interrupt status bit (1) interrupt status bit (2)** 0 0 fifos enabled ** fifos enabled ** + 2 u art fifo c ontrol r egister (write only) ufr fifo enable rcvr fifo reset xmit fifo reset dma mode select reserved reversed rx interrupt active level (lsb) rx interrupt active level (msb) + 3 u art c ontrol r egister ucr data length select bit 0 (dls0) data length select bit 1 (dls1) multiple stop bits enable (msbe) parity bit enable (pbe) even parity enable (epe) parity bit fixed enable pbfe) set silence enable (sse) baudrate divisor latch access bit (bdlab) + 4 h andshake c ontrol r egister hcr data terminal ready (dtr) request to send (rts) loopback ri input irq enable internal loopback enable 0 0 0 + 5 u art s tatus r egister usr rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) tbr empty (tbre) tsr empty (tsre) rx fifo error indication (rfei) ** + 6 h andshake s tatus r egister hsr cts toggling (tcts) dsr toggling (tdsr) ri falling edge (feri) dcd toggling (tdcd) clear to send (cts) data set ready (dsr) ring ind icator (ri) data carrier detect (dcd) + 7 u ser d efined r egister udr bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 + 0 bdlab = 1 b audrate d ivisor l atch l ow bll bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 + 1 bdlab = 1 b audrate d ivisor l atch h igh bhl bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 *: bit 0 is the least significant bit. the least significant bit is the first bit serially transmitted or received. **: these bits are always 0 in 16450 mode.
W83627SF preliminary publication release date: nov . 2000 - 49 - revision 0. 6 0 bit 4: epe. this bit describes the nu mber of logic 1's in the data word bits and parity bit only when bit 3 is programmed. when this bit is set, an even number of logic 1's are sent or checked. when the bit is reset, an odd number of logic 1's are sent or checked. bit 3: pbe. when this bit is set, the position between the last data bit and the stop bit of the sout will be stuffed with the parity bit at the transmitter. for the receiver, the parity bit in the same position as the transmitter will be detected. bit 2: msbe. this bit defines the n umber of stop bits in each serial character that is transmitted or received. (1) if msbe is set to a logical 0, one stop bit is sent and checked. (2) if msbe is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) if msbe is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. bits 0 and 1: dls0, dls1. these two bits define the number of data bits that are sent or checked in each serial character. table 4 - 2 word length d efinition dls1 dls0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits
W83627SF preliminary publication release date: nov . 2000 - 50 - revision 0. 6 0 4.2.2 uart status register (usr) (read/write) this 8 - bit register provides information about the status of the data transfer during communication. 1 2 3 4 5 6 7 0 rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) transmitter buffer register empty (tbre) transmitter shift register empty (tsre) rx fifo error indication (rfei) bit 7: rfei. in 16450 mode, this bit is always set to a logic 0. in 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the fifo. in 16550 mode, this bit is cleared by reading from the usr if there are no remaining errors left in the fifo. bit 6: tsre. in 16450 mode, when tbr and tsr are both empty, this bit will be set to a logical 1. in 16550 mode, if the transmit fifo and tsr are both empty, it will be set to a logical 1. other thanthese two cases, this bit will be reset to a logical 0. bit 5: tbre. in 16450 mode, when a data character is transferred from tbr to tsr, this bit will be set to a logical 1. if etrei of icr is a logical 1, an interrupt will be generated to notify the cpu to write the next dat a. in 16550 mode, this bit will be set to a logical 1 when the transmit fifo is empty. it will be reset to a logical 0 when the cpu writes data into tbr or fifo. bit 4: sbd. this bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 3: nser. this bit is se t to a logical 1 to indicate that the received data have no stop bit. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 2: pber. this bit is set to a logical 1 to indicate that the parity bit of received data is wrong. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 1: oer. this bit is set to a logical 1 to indica te received data have been overwritten by the next received data before they were read by the cpu. in 16550 mode, it indicates the same condition instead of fifo full. when the cpu reads usr, it will clear this bit to a logical 0. bit 0: rdr. this bit is set to a logical 1 to indicate received data are ready to be read by the cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0.
W83627SF preliminary publication release date: nov . 2000 - 51 - revision 0. 6 0 4.2.3 handshake control register (hcr) (read/write) this register controls the pins of the uart used for handshaking peripherals such as modem, and controls the diagnostic mode of the uart. 0 0 0 0 1 2 3 4 5 6 7 data terminal ready (dtr) request to send (rts) loopback ri input irq enable internal loopback enable bit 4: when this bit is set to a logical 1, the uart enters diagnostic mode by an internal loopback, as follows: (1) sout is forced to logical 1, and sin is isolated from the communication link instead of the tsr. (2) modem output pins are set to their inactive state. (3) modem input pins are isolated from the communication link and connect internally as dtr (bit 0 of hcr) ? dsr , rts ( bit 1 of hcr) ? cts , loopback ri input ( bit 2 of hcr) ? ri and irq enable ( bit 3 of hcr) ? dcd . aside from the above connections, the uart operates normally. this method allows the cpu to test the uart in a convenient way. bit 3: the uart interrupt output is enabled by setting this bit to a logic 1. in the diagnostic mode this bit is internally connected to the modem control input dcd . bit 2: this bit is used only in the diagnostic mode. in the diagnostic mode this bit is internally connected to the modem control input ri . bit 1: this bit controls the rts output. the value of this bit is inverted and output to rts . bit 0: this bit controls the dtr output. the value of this bit is inverted and output to dtr .
W83627SF preliminary publication release date: nov . 2000 - 52 - revision 0. 6 0 4.2.4 handshake status register (hsr) (read/write) this register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins. 1 2 3 4 5 6 7 0 ri falling edge (feri) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) cts toggling (tcts) dsr toggling (tdsr) dcd toggling (tdcd) bit 7: this bit is the opposite of the dcd input. this bit is equivalent to bit 3 of hcr in loopback mode. bit 6: thi s bit is the opposite of the ri input. this bit is equivalent to bit 2 of hcr in loopback mode. bit 5: this bit is the opposite of the dsr input. this bit is equivalent to bit 0 of hcr in loopback mode. bit 4: this bit is the opposite of the cts input. this bit is equivalent to bit 1 of hcr in loopback mode. bit 3: tdcd. this bit indicates that the dcd pin has changed state after hsr was read by the cpu. bit 2: feri. this bit indicates that the ri pin has changed from low to high state after hsr was read by the cpu. bit 1: tdsr. this bit indicates that the dsr pin has changed state after hsr was read by the cpu. bit 0: tcts. this bit indicates that the cts pin has changed state after hsr was read.
W83627SF preliminary publication release date: nov . 2000 - 53 - revision 0. 6 0 4.2.5 uart fifo control register (ufr) (write only) this register is used to control the fifo functions of the uart. 1 2 3 4 5 6 7 0 fifo enable receiver fifo reset transmitter fifo reset dma mode select reserved reserved rx interrupt active level (lsb) rx interrupt active level (msb) bit 6, 7: these two bits are used to set the active level for the receiver fifo interrupt. for example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in t he receiver fifo, the interrupt will be activated to notify the cpu to read the data from the fifo. table 4 - 3 fifo trigger level bit 7 bit 6 rx fifo interrupt ac tive level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 bit 4, 5: reserved bit 3: when this bit is programmed to logic 1, the dma mode will change from mode 0 to mode 1 if ufr bit 0 = 1. bit 2: setting this bit to a logical 1 resets the tx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a log ical 1. bit 1: setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. bit 0: this bit enables the 16550 (fifo) mode of the uart. this bit should be set to a logical 1 before other bits of ufr are programmed.
W83627SF preliminary publication release date: nov . 2000 - 54 - revision 0. 6 0 4.2.6 interrupt status register (isr) (read only) this register reflects the uart interrupt status, which is encoded by different interrupt sources into 3 bits. 1 2 3 4 5 6 7 0 0 if interrupt pending interrupt status bit 0 interrupt status bit 1 interrupt status bit 2 fifos enabled fifos enabled 0 0 bit 7, 6: these two bits are set to a l ogical 1 when ufr bit 0 = 1. bit 5, 4: these two bits are always logic 0. bit 3: in 16450 mode, this bit is 0. in 16550 mode, both bit 3 and 2 are set to a logical 1 when a time - out interrupt is pending. bit 2, 1: these two bits identify the priority level of the pending interrupt, as shown in the table below. bit 0: this bit is a logical 1 if there is no interrupt pending. if one of the interrupt sources has occurred, this bit will be set to a logical 0. table 4 - 4 interrupt control function isr interr upt set and function bit 3 bit 2 bit 1 bit 0 interrupt priority interrupt type interrupt source clear interrupt 0 0 0 1 - - no interrupt pending - 0 1 1 0 first uart receive status 1. oer = 1 2. pber =1 3. nser = 1 4. sbd = 1 read usr 0 1 0 0 second rbr data ready 1. rbr data ready 2. fifo interrupt active level reached 1. read rbr 2. read rbr until fifo data under active level 1 1 0 0 second fifo data timeout data present in rx fifo for 4 characters period of time since l ast access of rx fifo. read rbr 0 0 1 0 third tbr empty tbr empty 1. write data into tbr 2. read isr (if priority is third) 0 0 0 0 fourth handshake status 1. tcts = 1 2. tdsr = 1 3. feri = 1 4. tdcd = 1 read hsr ** bit 3 of isr is enabled when bit 0 of ufr is logical 1.
W83627SF preliminary publication release date: nov . 2000 - 55 - revision 0. 6 0 4.2.7 interrupt control register (icr) (read/write) this 8 - bit register allows the five types of controller interrupts to activate the interrupt output signal separately. the interrupt system can be totally disabled by resetti ng bits 0 through 3 of the interrupt control register (icr). a selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 0 0 0 1 2 3 4 5 6 7 0 0 rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) uart receive status interrupt enable (eusri) handshake status interrupt enable (ehsri) bit 7 - 4: these four bits are always logic 0. bit 3: ehsri. setting this bit to a logical 1 enables the handshake status register interrupt. bit 2: eusri. setting this bit to a logical 1 enables the uart status register interrupt. bit 1: etbrei. setting this bit to a logical 1 enables the tbr empty interrupt. bit 0: erdri. setting this bit to a logical 1 enables the rbr data ready interrupt. 4.2.8 programmable baud generator (bll/bhl) (read/write) two 8 - bit registers, bll and bhl, compose a programmable baud generator that uses 24 mhz to generate a 1.8461 mhz frequency and divides it by a divisor from 1 to 2 16 - 1. the output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. the table in the next page illustrates the use of the baud generator with a frequency of 1.846 1 mhz. in high - speed uart mode (refer to cr0c bit7 and cr0c bit6), the programmable baud generator directly uses 24 mhz and the same divisor as the normal speed divisor. in high - speed mode, the data transmission rate can be as high as 1.5m bps.
W83627SF preliminary publication release date: nov . 2000 - 56 - revision 0. 6 0 4.2.9 user - defined register (udr) (read/write) this is a temporary register that can be accessed and defined by the user. table 4 - 5 baud rate table baud rate from diffe rent pre - divider pre - div: 13 1.8461m hz pre - div:1.625 14.769m hz pre - div: 1.0 24m hz decimal divis or used to generate 16x clock error percentage between desired and actual 50 400 650 2304 ** 75 600 975 1536 ** 110 880 1430 1047 0.18% 134.5 1076 1478.5 857 0.099% 150 1200 1950 768 ** 300 2400 3900 384 ** 600 4800 7800 192 ** 1200 9600 15600 96 ** 1800 14400 23400 64 ** 2000 16000 26000 58 0.53% 2400 19200 31200 48 ** 3600 28800 46800 32 ** 4800 38400 62400 24 ** 7200 57600 93600 16 ** 9600 76800 124800 12 ** 19200 153600 249600 6 ** 38400 307200 499200 3 ** 57600 460800 748800 2 ** 115 200 921600 1497600 1 ** ** the percentage error for all baud rates, except where indicated otherwise, is 0.16%. note. pre - divisor is determined by crf0 of uart a and b.
W83627SF preliminary publication release date: nov. 2000 - 57 - revision 0.60 5. cir receiver port 5.1 cir registers 5.1.1 bank0.reg0 - receiver buffer registers (rbr) (read) receiver buffer register is read only. when the cir pulse train has been detected and passed by the internal signal filter, the data samped and shifted into shifter registe r will write into receiver buffer register. in the cir, this port is only supports pio mode and the address port is defined in the pnp. 5.1.2 bank0.reg1 - interrupt control register (icr) power on default <7:0> = 00000000 binary bit name read/write description 7 en_glbi read/write enable global interrupt. write 1, enable interrupt. write 0, disable global interrupt. 6 - 3 reserved - reserved 2 en_tmr_i read/write enable timer interrupt. 1 en_lsr_i read/write enable line - status - register interrupt. 0 en_rx_i rea d/write receiver thershold - level interrupt enable. 5.1.3 bank0.reg2 - interrupt status register (isr) power on default <7:0> = 00000000 binary bit name read/write description 7 - 3 reserved reserved 2 tmr_i read only timer interrupt. set to 1 when timer count to 0. this bit will be affected by (1) the timer registers are defined in bank4.reg0 and bank1.reg0~1, (2) en_tmr(enable timer, in bank0.reg3.bit2) should be set to 1, (3) entmr_i (enable timer interrupt, in bank0.reg1.bit2) should be set to 1. 1 lsr_i read only line - status - register interrupt. set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the line status register (lsr) sets to 1. clear to 0 when lsr is read. 0 rxth_i read only receiver thershold - level interrupt. se t to 1 when (1) the receiver buffer register (rbr) is equal or larger than the threshold level, (2) rbr occurs time - out if the receiver buffer register has valid data and below the threshold level. clear to 0 when rbr is less than threshold level from read ing rbr.
W83627SF preliminary publication release date: nov. 2000 - 58 - revision 0.60 5.1.4 bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) power on default <7:0> = 00000000 binary bit name read/write description 7 - 6 bnk_sel<1:0> read/write bank select register. these two bits are shared same address s o that bank select register (bsr) can be programmed to desired bank in any bank. bnk_sel<1:0> = 00 select bank 0. bnk_sel<1:0> = 01 select bank 1. bnk_sel<1:0> = reserved. bnk_sel<1:0> = reserved. 5 - 4 rxftl1/0 read/write receiver fifo threshold level. it is to determine the rxth_i to become 1 when the receiver fifo threshold level is equal or larger than the defined value shown as follow. rxftl<1:0> = 00 -- 1 byte rxftl<1:0> = 01 -- 4 bytes rxftl<1:0> = 10 -- 8 bytes rxftl<1:0> = 11 -- 14 bytes 3 tmr_tst read/write timer test. write to 1, then reading the tmrl/tmrh will return the programmed values of tmrl/tmrh, that is, does not return down count counter value. this bit is for test timer register. 2 en_tmr read/write enable timer. write to 1, enable the timer 1 rxf_rst read/write setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. 0 tmr_clk read/write timer input clock. winbond test register 5.1.5 bank 0.reg4 - cir control register (ctr) power on default <7:0> = 0010,1001 binary bit name read/write description 7 - 5 rx_fr<2:0> read/write receiver frequency range 2~0. these bits select the input frequency of the receiver ranges. for the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. 4 - 0 rx_fsl<4:0> read/write receiver frequency select 4~0. select the receiver operation frequency.
W83627SF preliminary publication release date: nov. 2000 - 59 - revision 0.60 table: low frequ ency range select of receiver. rx_fr2~0 (low frequency) 001 010 011 rx_fsl4~0 min. max. min. max. min. max. 00010 26.1 29.6 24.7 31.7 23.4 34.2 00011 28.2 32.0 26.7 34.3 25.3 36.9 00100 29.4 33.3 27.8 35.7 26.3 38.4 00101 30.0 34.0 28.4 36.5 26.9 3 9.3 00110 31.4 35.6 29.6 38.1 28.1 41.0 00111 32.1 36.4 30.3 39.0 28.7 42.0 01000 32.8 37.2 31.0 39.8 29.4 42.9 01001 33.6* 38.1* 31.7 40.8 30.1 44.0 01011 34.4 39.0 32.5 41.8 30.8 45.0 01100 36.2 41.0 34.2 44.0 32.4 47.3 01101 37.2 42.1 35.1 45.1 3 3.2 48.6 01111 38.2 43.2 36.0 46.3 34.1 49.9 10000 40.3 45.7 38.1 49.0 36.1 52.7 10010 41.5 47.1 39.2 50.4 37.2 54.3 10011 42.8 48.5 40.4 51.9 38.3 56.0 10101 44.1 50.0 41.7 53.6 39.5 57.7 10111 45.5 51.6 43.0 55.3 40.7 59.6 11010 48.7 55.2 46.0 59. 1 43.6 63.7 11011 50.4 57.1 47.6 61.2 45.1 65.9 11101 54.3 61.5 51.3 65.9 48.6 71.0 note that the other non - defined values are reserved. 5.1.6 bank0.reg5 - uart line status register (usr) power on default <7:0> = 0000,0000 binary bit name read/write descrip tion 7 - 3 reserved - - 2 rx_to read/write set to 1 when receiver fifo or frame status fifo occurs time - out. read this bit will be cleared. 1 ov_err read/write received fifo overrun. read to clear. 0 rdr read/write this bit is set to a logical 1 to indic ate received data are ready to be read by the cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0.
W83627SF preliminary publication release date: nov. 2000 - 60 - revision 0.60 5.1.7 bank0.reg6 - remote infrared config register (rir_cfg) power on default <7:0> = 0000,0000 binary bit n ame read/write description 7 - 6 smpsel<1:0> read/write sampling mode select. select internal decoder methodology from the internal filter. selected decoder mode will determine the receive data format. the sampling mode is shown as bellow: smpsel<1:0> = 00 t - period sample mode. smpsel<1:0> = 01 over - sampling mode. smpsel<1:0> = 10 over - sampling with re - sync. smpsel<1:0> = 11 fifo test mode. the t - period code format is defined as follows. the bit value is set to 0, then the high pulse will be received. the bit value is set to 1, then no energy will be received. the opposite results will be generated when the bit rxinv (bank0.reg6.bit0) is set to 1. 5 - 4 lp_sl<1:0> read/write low pass filter source selcetion. lp_sl<1:0> = 00 select raw irrx signal. lp_sl<1:0 > = 01 select r.b.p. signal lp_sl<1:0> = 10 select d.b.p. signal. lp_sl<1:0> = 11 reserved. 3 - 2 rxdmsl<1:0> read/write receiver demodulation source selection. rxdmsl<1:0> = 00 select b.p. and l.p. filter. rxdmsl<1:0> = 01 select b.p. but not l.p. rxdmsl< 1:0> = 10 reserved. rxdmsl<1:0> = 11 do not pass demodulation. 1 pre_div read/write baud rate pre - divisor. set to 1, the baud rate generator input clock is set to 1.8432m hz which is set to pre - divisor into 13. when set to 0, the pre - divisor is set to 1, that is, the input clock of baud rate generator is set to 24m hz. 0 rxinv read/write receiving signal invert. write to 1, invert the receiving signal. b7 b6 b5 b4 b2 b1 b0 b3 bit value ( number of bits) - 1
W83627SF preliminary publication release date: nov. 2000 - 61 - revision 0.60 5.1.8 bank0.reg7 - user defined register (udr/audr) power on default <7:0> = 0000,0000 binary bit name read /write description 7 rxact read/write receive active. set to 1 whenever a pulse or pulse - train is detected by the receiver. if a 1 is written into the bit position, the bit is cleared and the receiver is de - actived. when this bit is set, the receiver samp les the ir input continuously at the programmed baud rate and transfers the data to the receiver fifo. 6 rx_pd read only set to 1 whenever a pulse or pulse - train (modulated pulse) is detected by the receiver. can be used by the sofware to detect idle cond ition cleared upon read. 5 reserved - - 4 - 0 folval read only fifo level value. indicate that how many bytes are there in the current received fifo. can read these bits then get the fifo level value and successively read rbr by the prior value.
W83627SF preliminary publication release date: nov. 2000 - 62 - revision 0.60 5.1.9 bank1.r eg0~1 - baud rate divisor latch (bll/bhl) the two registers of bll and bhl are baud rate divisor latch in the legacy uart/sir/ask - ir mode. read/write these registers, if set in advanced uart mode, will occur backward operation, that is, will go to legacy u art mode and clear some register values shown table as follows. table :baud rate table baud rate using 24 m hz to generate 1.846 1 mhz desired baud rate decimal divisor used to generate 16x clock percent error difference between desired and actual 50 23 04 ** 75 1536 ** 110 1047 0.18% 134.5 857 0.099% 150 768 ** 300 384 ** 600 192 ** 1200 96 ** 1800 64 ** 2000 58 0.53% 2400 48 ** 3600 32 ** 4800 24 ** 7200 16 ** 9600 12 ** 19200 6 ** 38400 3 ** 57600 2 ** 115200 1 ** 1.5m 1 note 1 0% note 1: only use in high speed mode, when bank0.reg6.bit7 is set. ** the percentage error for all baud rates, except where indicated otherwise, is 0.16%
W83627SF preliminary publication release date: nov. 2000 - 63 - revision 0.60 5.1.10 bank1.reg2 - version id regiister i (vid) power on default <7:0> = 0001,0000 binary bit name re ad/write description 7 - 0 vid read only version id, default is set to 0x10. 5.1.11 bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) this register is defined same as in bank0.reg3. 5.1.12 bank1.reg4 - timer low byte register (tmrl) pow er on default <7:0> = 0000,0000 binary bit name read/write description 7 - 0 tmrl read/write timer low byte register. this is a 12 - bit timer (another 4 - bit is defined in bank1.reg5) which resolution is 1 ms, that is, the programmed maximum time is 2 12 - 1 ms. the timer is a down - counter. the timer start down count when the bit en_tmr (enable timer) of bank0.reg2. is set to 1. when the timer down count to zero and en_tmr=1, the tmr_i is set to 1. when the counter down count to zero, a new initial value will be re - loaded into timer counter. 5.1.13 bank1.reg5 - timer high byte register (tmrh) power on default <7:0> = 0000,0000 binary bit name read/write description 7 - 4 reserved reserved. 3 - 0 tmrh read/write timer high byte register. see bank1.reg4.
W83627SF preliminary publication release date: nov. 2000 - 64 - revision 0.60 6. parallel port 6.1 printer interface logic the parallel port of the W83627SF makes possible the attachment of various devices that accept eight bits of parallel data at standard ttl level. the W83627SF supports an ibm xt/at compatible parallel port (spp), bi - directional pa rallel port (bpp), enhanced parallel port (epp), extended capabilities parallel port (ecp), extension fdd mode (extfdd), extension 2fdd mode (ext2fdd) on the parallel port. refer to the configuration registers for more information on disabling, power - down , and on selecting the mode of operation. table 6 - 1 shows the pin definitions for different modes of the parallel port. table 6 - 1 - 1 parallel port connector and pin definitions host connector pin number of W83627SF pin attribute spp epp ecp 1 36 o nstb nwrite nstb, hostclk 2 2 - 9 31 - 26, 24 - 23 i/o pd<0:7> pd<0:7> pd<0:7> 10 22 i nack intr nack, periphclk 2 11 21 i busy nwait busy, periphack 2 12 19 i pe pe peerror, nackreverse 2 13 18 i slct select slct, xflag 2 14 35 o nafd ndstrb nafd, hostack 2 15 34 i nerr nerror nfault 1 , nperiphrequest 2 16 33 o ninit ninit ninit 1 , nreverserqst 2 17 32 o nslin nastrb nslin 1 , ecpmode 2 notes: n : active low 1. compatible mode 2. high speed mode 3. for more information, refer to the ieee 1284 standard.
W83627SF preliminary publication release date: nov. 2000 - 65 - revision 0.60 table 6 - 1 - 2 parallel port connector and pin definitions host connector pin number of W83627SF pin attribute spp pin attribute ext2fdd pin attribute extfdd 1 36 o nstb --- --- --- --- 2 31 i/o pd0 i index2# i index2# 3 30 i/o pd1 i trak02# i trak02# 4 29 i/o pd2 i wp2# i wp2# 5 28 i/o pd3 i rdata2# i rdata2# 6 27 i/o pd4 i dskchg2# i dskchg2# 7 26 i/o pd5 --- --- --- --- 8 24 i/o pd6 od moa2# --- --- 9 23 i/o pd7 od dsa2# --- --- 10 22 i nack od dsb2# od dsb2# 11 21 i busy od mob2# od mob2# 12 19 i pe od wd2# od wd2# 13 18 i slct od we2# od we2# 14 35 o nafd od rwc2# od rwc2# 15 34 i nerr od head2# od head2# 16 33 o ninit od dir2# od dir2# 17 32 o nslin od step2# od step2# 6.2 enhanced parallel port (epp) table 6 - 2 printer mode and epp regist er address a2 a1 a0 register note 0 0 0 data port (r/w) 1 0 0 1 printer status buffer (read) 1 0 1 0 printer control latch (write) 1 0 1 0 printer control swapper (read) 1 0 1 1 epp address port (r/w) 2 1 0 0 epp data port 0 (r/w) 2 1 0 1 epp data p ort 1 (r/w) 2 1 1 0 epp data port 2 (r/w) 2 1 1 1 epp data port 2 (r/w) 2 notes: 1. these registers are available in all modes. 2. these registers are available only in epp mode.
W83627SF preliminary publication release date: nov. 2000 - 66 - revision 0.60 6.2.1 data swapper the system microprocessor can read the contents of the prin ter's data latch by reading the data swapper. 6.2.2 printer status buffer the system microprocessor can read the printer status by reading the address of the printer status buffer. the bit definitions are as follows: 1 1 1 2 3 5 4 6 7 0 tmout error slct pe busy ack bit 7: this signal is active during data entry, when the printer is off - line during printing, when the print head is changing position, or during an error state. when this signal is active, the printer is busy and cannot accept data. bit 6: this bit rep resents the current state of the printer's ack# signal. a 0 means the printer has received a character and is ready to accept another. normally, this signal will be active for approximately 5 microseconds before busy# stops. bit 5: logical 1 means the pri nter has detected the end of paper. bit 4: logical 1 means the printer is selected. bit 3: logical 0 means the printer has encountered an error condition. bit 1, 2: these two bits are not implemented and are logic one during a read of the status register. bit 0: this bit is valid in epp mode only. it indicates that a 10 m s time - out has occurred on the epp bus. a logic 0 means that no time - out error has occurred; a logic 1 means that a time - out error has been detected. writing a logic 1 to this bit will cl ear the time - out status bit; writing a logic 0 has no effect.
W83627SF preliminary publication release date: nov. 2000 - 67 - revision 0.60 6.2.3 printer control latch and printer control swapper the system microprocessor can read the contents of the printer control latch by reading the printer control swapper. bit definitions are as fo llows: 1 1 1 2 3 4 5 6 7 0 strobe auto fd slct in irq enable dir init bit 7, 6: these two bits are a logic one during a read. they can be written. bit 5: direction control bit when this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, t he parallel port is in output mode (write). this bit can be read and written. in spp mode, this bit is invalid and fixed at zero. bit 4: a 1 in this position allows an interrupt to occur when ack# changes from low to high. bit 3: a 1 in this bit positi on selects the printer. bit 2: a 0 starts the printer (50 microsecond pulse, minimum). bit 1: a 1 causes the printer to line - feed after a line is printed. bit 0: a 0.5 microsecond minimum high active pulse clocks data into the printer. valid data must b e present for a minimum of 0.5 microseconds before and after the strobe pulse. 6.2.4 epp address port the address port is available only in epp mode. bit definitions are as follows: 1 2 3 4 5 6 7 0 pd0 pd1 pd2 pd3 pd5 pd4 pd6 pd7
W83627SF preliminary publication release date: nov. 2000 - 68 - revision 0.60 the contents of db0 - db7 are buf fered (non - inverting) and output to ports pd0 - pd7 during a write operation. the leading edge of iow# c auses an epp address write cycle to be performed, and the trailing edge of iow# latches the data for the duration of the epp write cycle. pd0 - pd7 ports are read during a read operation. the leading edge of ior# causes an epp address read cycle to be performed and the data to be output to the host cpu. 6.2.5 epp data port 0 - 3 these four registers are available only in epp mode. bit definitions of each data por t are as follows: 1 2 3 4 5 6 7 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 when accesses are made to any epp data port, the contents of db0 - db7 are buffered (non - inverting) and output to the ports pd0 - pd7 during a write operation. the leading edge of iow# causes an e pp data write cycle to be performed, and the trailing edge of iow# latches the data for the duration of the epp write cycle. during a read operation, ports pd0 - pd7 are read, and the leading edge of ior# causes an epp read cycle to be performed and the dat a to be output to the host cpu. 6.2.6 bit map of parallel port and epp registers register 7 6 5 4 3 2 1 0 data port (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 status buffer (read) busy# ack# pe slct errof# 1 1 tmout control swapper (read) 1 1 1 irqen slin init# au tofd# strobe# control latch (write) 1 1 dir irq slin init# autofd# strobe# epp address port r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 0 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 1 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data por t 2 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 3 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0
W83627SF preliminary publication release date: nov. 2000 - 69 - revision 0.60 6.2.7 epp pin descriptions epp name type epp description nwrite o denotes an address or data read or write operation. pd<0:7> i/o bi - directional epp address and data bus. intr i used by peripheral device to interrupt the host. nwait i inactive to acknowledge that data transfer is completed. active to indicate that the device is ready for the next transfer. pe i paper end; same as spp mode. select i printer se lected status; same as spp mode. ndstrb o this signal is active low. it denotes a data read or write operation. nerror i error; same as spp mode. ninits o this signal is active low. when it is active, the epp device is reset to its initial operating mod e. nastrb o this signal is active low. it denotes an address read or write operation. 6.2.8 epp operation when the epp mode is selected in the configuration register, the standard and bi - directional modes are also available. the pdx bus is in the standard or b i - directional mode when no epp read, write, or address cycle is currently being executed. in this condition all output signals are set by the spp control port and the direction is controlled by dir of the control port. a watchdog timer is required to prev ent system lockup. the timer indicates that more than 10 m s have elapsed from the start of the epp cycle to the time wait# is deasserted. the current epp cycle is aborted when a time - out occurs. the time - out condition is indicated in status bit 0. 6.2.8.1 epp oper ation the epp operates on a two - phase cycle. first, the host selects the register within the device for subsequent operations. second, the host performs a series of read and/or write byte operations to the selected register. four operations are supported o n the epp: address write, data write, address read, and data read. all operations on the epp device are performed asynchronously. 6.2.8.2 epp version 1.9 operation the epp read/write operation can be completed under the following conditions: a. if the nwait is act ive low, when the read cycle (nwrite inactive high, ndstrb/nastrb active low) or write cycle (nwrite active low, ndstrb/nastrb active low) starts, the read/write cycle proceeds normally and will be completed when nwait goes inactive high. b. if nwait is in active high, the read/write cycle will not start. it must wait until nwait changes to active low, at which time it will start as described above. 6.2.8.3 epp version 1.7 operation the epp read/write cycle can start without checking whether nwait is active or inact ive. once the read/write cycle starts, however, it will not terminate until nwait changes from active low to inactive high.
W83627SF preliminary publication release date: nov. 2000 - 70 - revision 0.60 6.3 extended capabilities parallel (ecp) port this port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ecp is not required. it provides an automatic high burst - bandwidth channel that supports dma for ecp in both the forward (host to peripheral) and reverse (peripheral to host) directions. small fifos are used in both for ward and reverse directions to improve the maximum bandwidth requirement. the size of the fifo is 16 bytes. the ecp port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the ecp port supports run - length - encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. hardware support for compression is optional. for more information about the ecp protocol, refer to the extended capabilities port protocol and isa interface standard. 6.3.1 ecp register and mode definitions name address i/o ecp modes function data base+000h r/w 000 - 001 data register ecpafifo base+000h r/w 011 ecp fifo (address) dsr base+001h r all status register dcr base+002h r/w all control register cfifo base+400h r/w 010 parallel port data fifo ecpdfifo base+400h r/w 011 ecp fifo (data) tfifo base+400h r/w 110 test fifo cnfga base+400h r 111 confi guration register a cnfgb base+401h r/w 111 configuration register b ecr base+402h r/w all extended control register note: the base addresses are specified by cr23, which are determined by configuration register or hardware setting. mode description 0 00 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the cr9 and cr0 to select ecp/epp mode) 101 reserved 110 test mode 111 configuration mode note: the mode selection bits are bit 7 - 5 of the extended control register.
W83627SF preliminary publication release date: nov. 2000 - 71 - revision 0.60 6.3.2 data and ecpafifo port modes 000 (spp) and 001 (ps/2) (data port) during a write operation, the data register latches the contents of the data bus on the rising edge of the input. the conten ts of this register are output to the pd0 - pd7 ports. during a read operation, ports pd0 - pd7 are read and output to the host. the bit definitions are as follows: 7 6 5 4 3 2 1 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 mode 011 (ecp fifo - address/rle) a data byte writt en to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peripheral automatically. the operation of this register is defined only for the forward direction. the bit definitions are a s follows: 7 6 5 4 3 2 1 0 address or rle address/rle 6.3.3 device status register (dsr) these bits are at low level during a read of the printer status register. the bits of this status register are defined as follows: 7 6 5 4 3 2 1 0 nfault select perror nack nbusy 1 1 1
W83627SF preliminary publication release date: nov. 2000 - 72 - revision 0.60 bit 7: this bit reflects the complement of the busy input. bit 6: this bit reflects the nack input. bit 5: this bit reflects the perror input. bit 4: this bit reflects the select input. bit 3: this bit reflects the nfault input. bit 2 - 0: these three bits are not implemented and are always logic one during a read. 6.3.4 device control register (dcr) the bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 strobe autofd ninit selectin ackinten direction bit 6, 7: these two bits are logic one during a read and cannot be written. bit 5: this bit has no effect and the direction is always out if mode = 000 or mode = 010. direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. bit 4: interrupt request enable. when this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the ack# input. bit 3: this bit is inverted and output to the slin# output. 0 the printer is not selected. 1 the printer is selected. bit 2: this bit is output to the init# output. bit 1: this bit is inverted and output to the afd# output. bit 0: this bit is inverted and output to the stb# output.
W83627SF preliminary publication release date: nov. 2000 - 73 - revision 0.60 6.3.5 cfifo (parallel port data fifo) mode = 010 this mode is defin ed only for the forward direction. the standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or dmaed from the system to this fifo. transfers to the fifo are byte aligned. 6.3.6 ecpdfifo (ecp data fifo) mode = 011 when the direction bit is 0, bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. when the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ecp into this fifo. reads or dmas from the fifo will return bytes of ecp data to the system. 6.3.7 tfifo (test fifo mode) mode = 110 data bytes may be read, written, or dmaed to or fro m the system to this fifo in any direction. data in the tfifo will not be transmitted to the parallel port lines. however, data in the tfifo may be displayed on the parallel port data lines. 6.3.8 cnfga (configuration register a) mode = 111 this register is a read - only register. when it is read, 10h is returned. this indicates to the system that this is an 8 - bit implementation. 6.3.9 cnfgb (configuration register b) mode = 111 the bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 1 intrvalue compress irqx 0 irqx 1 irqx 2 bit 7: this bit is read - only. it is at low level during a read. this means that this chip does not support hardware rle compression. bit 6: returns the value on the isa irq line to determine possible conflicts.
W83627SF preliminary publication release date: nov. 2000 - 74 - revision 0.60 bit 5 - 3: reflect the irq resource assigned fo r ecp port. cnfgb[5:3] irq resource 000 reflect other irq resources selected by pnp register (default) 001 irq7 010 irq9 011 irq10 100 irq11 101 irq14 110 irq15 111 irq5 bit 2 - 0: these five bits are at high level during a read and can be written . 6.3.10 ecr (extended control register) mode = all this register controls the extended ecp parallel port functions. the bit definitions are follows: 7 6 5 4 3 2 1 0 empty full service intr dmaen nerrintren mode mode mode bit 7 - 5: these bits are read/write and select the mode. 000 standard parallel port mode. the fifo is reset in this mode. 001 ps/2 parallel port mode. this is the same as 000 except that direction may be used to tri - state the data lines and reading the data register returns the value on the data lines and not the value in the data register. 010 parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data are automatically transmitted using the standard parallel port protocol. this mode is useful only when direction is 0. 011 ecp parallel port mode. when the direction is 0 (forward direction), bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and auto transmitted to the peripheral using ecp protocol. when the direction is 1 (reverse direction), bytes a re moved from the ecp parallel port and packed into bytes in the ecpdfifo. 100 selects epp mode. in this mode, epp is activated if the epp mode is selected. 101 reserved. 110 test mode. the fifo may be written and read in this mode, but the data will no t be transmitted on the parallel port. 111 configuration mode. the confga and confgb registers are accessible at 0x400 and 0x401 in this mode.
W83627SF preliminary publication release date: nov. 2000 - 75 - revision 0.60 bit 4: read/write (valid only in ecp mode) 1 disables the interrupt generated on the asserting edge of nfault . 0 enables an interrupt pulse on the high to low edge of nfault. if nfault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. bit 3: read/write 1 enables dma. 0 disables dma unconditionally. bit 2: re ad/write 1 disables dma and all of the service interrupts. 0 enables one of the following cases of interrupts. when one of the service interrupts has occurred, the serviceintr bit is set to a 1 by hardware. this bit must be reset to 0 to re - enable the int errupts. writing a 1 to this bit will not cause an interrupt. (a) dmaen = 1: during dma this bit is set to a 1 when terminal count is reached. (b) dmaen = 0 direction = 0: this bit is set to 1 whenever there are writeintr threshold or more bytes free in the fifo. (c) dmaen = 0 direction = 1: this bit is set to 1 whenever there are readintr threshold or more valid bytes to be read from the fifo. bit 1: read only 0 the fifo has at least 1 free byte. 1 the fifo cannot accept another byte or the fifo i s completely full. bit 0: read only 0 the fifo contains at least 1 byte of data. 1 the fifo is completely empty. 6.3.11 bit map of ecp port registers d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 1 1 1 1 dcr 1 1 directio ackinten selectin ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue 1 1 1 1 1 1 ecr mode nerrintren dmaen serviceintr full empty notes: 1. these registers are available in all modes. 2. all fifos use one common 16 - byte fifo.
W83627SF preliminary publication release date: nov. 2000 - 76 - revision 0.60 6.3.12 ecp pin descriptions name type description nstrobe (hostclk) o the nstrobe registers data or address into the slave on the asserting edge during write operations. this signal handshakes with busy. pd<7:0> i/o these signals contains address or data or rle data. nack (periphclk) i this signal indicates valid data driven by the peripheral when asserted. this signal hand shakes with nautofd in reverse. busy (periphack) i this signal deasserts to indicate that the peripheral can accept data. it indicates whether the data lines contain ecp command information or data in the reverse direction. when in reverse direction, norm al data are transferred when busy (periphack) is high and an 8 - bit command is transferred when it is low. perror (nackreverse) i this signal is used to acknowledge a change in the direction of the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select (xflag) i indicates printer on line. nautofd (hostack) o requests a byte of data from the peripheral when it is as serted. this signal indicates whether the data lines contain ecp address or data in the forward direction. when in forward direction, normal data are transferred when nautofd (hostack) is high and an 8 - bit command is transferred when it is low. nfault (np eriphrequest) i generates an error interrupt when it is asserted. this signal is valid only in the forward direction. the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ecp mode. ninit (nreversereques t) o this signal sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. nselectin (ecpmode) o this signal is always deasserted in ecp mode.
W83627SF preliminary publication release date: nov. 2000 - 77 - revision 0.60 6.3.13 ecp operation the host mus t negotiate on the parallel port to determine if the peripheral supports the ecp protocol before ecp operation. after negotiation, it is necessary to initialize some of the port bits. the following are required: (a) set direction = 0, enabling the drivers. (b) set strobe = 0, causing the nstrobe signal to default to the deasserted state. (c) set autofd = 0, causing the nautofd signal to default to the deasserted state. (d) set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo, respectively. 6.3.13.1 mode switching software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (mode 011 or 010). if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switc hed into mode 000 or 001. the direction can be changed only in mode 001. when in extended forward mode, the software should wait for the fifo to be empty before switching back to mode 000 or 001. in ecp reverse mode the software waits for all the data to b e read from the fifo before changing back to mode 000 or 001. 6.3.13.2 command/data ecp mode allows the transfer of normal 8 - bit data or 8 - bit commands. in the forward direction, normal data are transferred when hostack is high and an 8 - bit command is transferred w hen hostack is low. the most significant bits of the command indicate whether it is a run - length count (for compression) or a channel address. in the reverse direction, normal data are transferred when periphack is high and an 8 - bit command is transferred when periphack is low. the most significant bit of the command is always zero. 6.3.13.3 data compression the W83627SF supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. note that the odd (rle) compression i n hardware is not supported. in order to transfer data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. 6.3.14 fifo operation the fifo threshold is set in configuration register 5. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non - dma) mode, as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. after a reset, the fifo is disabled.
W83627SF preliminary publication release date: nov. 2000 - 78 - revision 0.60 6.3.15 dma transfers dma transfers are always to or from the ecpdfifo, tfifo, or cfifo. the dma uses the standard pc dma services. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and serviceintr is asserted, which will disable the dma. 6.3.16 programmed i/o (non - dma) mode the ecp or parallel port fifos can also be operated using interrupt driven program med i/o. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. the host must set the direction, state, dmaen = 0 and serviceintr = 0 in the programmed i/o transfers. th e ecp requests programmed i/o transfers from the host by activating the irq pin. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. 6.4 extension fdd mode (extfdd) in this mode, the W83627SF changes the printer interface pins to fdc input/output pins, allowing the user to install a second floppy disk drive (fdd b) through the db - 25 printer connector. the pin assignments for the fdc input/output pins are shown in table 6 - 1. after the printer interface is set to extfdd mode , the following occur: (1) pins mob# and dsb# will be forced to inactive state. (2) pins dskchg# , rdata# , wp# , trak0# , index# will be logically ored with pins pd4 - pd0 to serve as input signals to the fdc. (3) pins pd4 - pd0 each will have an internal resis tor of about 1k ohm to serve as pull - up resistor for fdd open drain/collector output. (4) if the parallel port is set to extfdd mode after the system has booted dos or another operating system, a warm reset is needed to enable the system to recognize the e xtension floppy drive.
W83627SF preliminary publication release date: nov. 2000 - 79 - revision 0.60 6.5 extension 2fdd mode (ext2fdd) in this mode, the W83627SF changes the printer interface pins to fdc input/output pins, allowing the user to install two external floppy disk drives through the db - 25 printer connector to replace int ernal floppy disk drives a and b. the pin assignments for the fdc input/output pins are shown in table6 - 1. after the printer interface is set to extfdd mode, the following occur: (1) pins moa# , dsa# , mob# , and dsb# will be forced to inactive state. (2) pi ns dskchg# , rdata# , wp# , trak0# , and index# will be logically ored with pins pd4 - pd0 to serve as input signals to the fdc. (3) pins pd4 - pd0 each will have an internal resistor of about 1k ohm to serve as pull - up resistor for fdd open drain/collector outpu t. (4) if the parallel port is set to ext2fdd mode after the system has booted dos or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
W83627SF preliminary publication release date: nov. 2000 - 80 - revision 0.60 7. keyboard controller the kbc (8042 with licensed kb bios) c ircuit of W83627SF is designed to provide the functions needed to interface a cpu with a keyboard and/or a ps/2 mouse, and can be used with ibm - compatible personal computers or ps/2 - based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. then, the controller will asserts an interrupt to the system when data are placed in its output buffer. the keyboard and ps/2 mouse are required to acknowledge all data transmissions. no transmission should be sent to the keyboard or ps/2 mouse until an acknowledge is received for the previous data byte. 8042 p 2 4 p 2 5 p 2 1 p 2 0 p 2 7 p 1 0 p 2 6 t 0 p 2 3 t 1 p 2 2 p 1 1 k i r q m i r q g a t e a 2 0 k b r s t p 1 7 k i n h g p i / o p i n s p 1 2 ~ p 1 6 k d a t k c l k m c l k m d a t m u l t i p l e x i / o p i n s keyboard and mouse interface
W83627SF preliminary publication release date: nov. 2000 - 81 - revision 0.60 7.1 output buffer the output buffer is an 8 - bit read - only register at i/o address 60h (default, pnp programmable i/o address ld5 - cr60 and ld5 - cr61). the keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. the output buffer can only be read when the output buffer full bit in the register is "1". 7.2 input buffer the input buffer is an 8 - bit write - only register at i/o address 60h or 64h (default, pnp programmable i/o address ld5 - cr60, ld5 - cr61, ld5 - cr62, and ld5 - cr63). writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard (unless the keyboard controller is expecting a data byte ) through the controller's input buffer only if the input buffer full bit in the status register is ? 0 ? . 7.3 status register the status register is an 8 - bit read - only register at i/o address 64h (default, pnp programmable i/o address ld5 - cr62 and ld5 - cr63), t hat holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: inp ut buffer full 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. it defaults to 0 after a power - on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboa rd is inhibited 1: keyboard is not inhibited 5 auxiliary device output buffer 0: auxiliary device output buffer empty 1: auxiliary device output buffer full 6 general purpose time - out 0: no time - out error 1: time - out error 7 parity error 0: odd parity 1 : even parity (error)
W83627SF preliminary publication release date: nov. 2000 - 82 - revision 0.60 7.4 commands command function 20h read command byte of keyboard controller 60h write command byte of keyboard controller bit 1 2 3 4 5 6 7 0 bit definition reserved ibm keyboard translate mode disable auxiliary device disable keyboard reserve system flag enable auxiliary interrupt enable keyboard interrupt a4h test password returns 0fah if password is loaded retu rns 0f1h if password is not loaded a5h load password load password until a "0" is received from the system a6h enable password enable the checking of keystrokes for a match with the password a7h disable auxiliary device interface a8h enable auxiliary d evice interface a9h interface test bit 04 03 02 01 00 bit definition no error detected auxiliary device "clock" line is stuck low auxiliary device "clock" line is stuck high auxiliary device "data" line is stuck low auxiliary device "data" line is stuck low
W83627SF preliminary publication release date: nov. 2000 - 83 - revision 0.60 7.4 commands, continued command function aah self - test returns 055h if self test succeeds abh interface test bit 04 03 02 01 00 bit definition no error detected keyboard "clock" line is stuck low keyboard "clock" line is stuck high keyboard "data" line is stuck low keyboard "data" line is stuck high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bits of port1 into status register c2h continuously puts the upper four bits of port1 into status register d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from auxiliary device d4h output next receiv ed byte of data from system to auxiliary device e0h reports the status of the test inputs fxh pulse only rc(the reset line) low for 6 m s if command byte is even
W83627SF preliminary publication release date: nov. 2000 - 84 - revision 0.60 7.5 hardware gatea20/keyboard reset control logic the kbc implements a hardware control logic to speed - up gatea20 and kbreset. this control logic is controlled by ld5 - crf0 as follows: 7.5.1 kb control register (logic device 5, cr - f0) bit 7 6 5 4 3 2 1 0 name kclks1 kclks0 reserved reserved reserved p92en hga20 hkbrst kclks1, kclks0 this 2 bits are for t he kbc clock rate selection. = 0 0 kbc clock input is 6 mhz = 0 1 kbc clock input is 8 mhz = 1 0 kbc clock input is 12 mhz = 1 1 kbc clock input is 16 mhz p92en (port 92 enable) a "1" on this bit enables port 92 to control gatea20 and kbreset. a "0 " on this bit disables port 92 functions. hga20 (hardware gate a20) a "1" on this bit selects hardware gatea20 control logic to control gate a20 signal. a "0" on this bit disables hardware gatea20 control logic function. hkbrst (hardware keyboard reset) a "1" on this bit selects hardware kb reset control logic to control kbreset signal. a "0" on this bit disable hardware kb reset control logic function. when the kbc receives a data follows a "d1" command, the hardware control logic sets or clears gate a20 a ccording to the received data bit 1. similarly, the hardware control logic sets or clears kbreset depending on the received data bit 0. when the kbc receives a "fe" command, the kbreset is pulse low for 6 m s(min.) with 14 m s(min.) delay. gatea20 and kbrese t are controlled by either the software control or the hardware control logic and they are mutually exclusive. then, gatea20 and kbreset are merged along with port92 when p92en bit is set. 7.5.2 port 92 control register (default value = 0x24) bit 7 6 5 4 3 2 1 0 name res. (0) res. (0) res. (1) res. (0) res. (0) res. (1) sga20 plkbrst sga20 (special gate a20 control) a "1" on this bit drives gate a20 signal to high. a "0" on this bit drives gate a20 signal to low. plkbrst (pull - low kbreset) a "1" on this bit ca uses kbreset to drive low for 6 m s(min.) with 14 m s(min.) delay. before issuing another keyboard reset command, the bit must be cleared.
W83627SF preliminary publication release date: nov. 2000 - 85 - revision 0.60 8. general purpose i/o W83627SF provides 42 input/output ports that can be individually configured to perform a simple ba sic i/o function or a pre - defined alternate function. these 42 gp i/o ports are divided into seven groups. gp1 is configured through control registers in logical device 7, gp2 in logical device 8, gp3 and gp4 in logical device 9, gp5, gp6, and gp7 in log ical device c. users can configure each individual port to be an input or output port by programming respective bit in i/o selection register (0 = output, 1 = input). invert port value by setting inversion register (0 = non - inverse, 1 = inverse). port v alue is read/written through data register. table 8.1 and 8.2 gives more details on gpio's assignment. in addition, gp3 and gp4 are designed to be functional even in power loss condition (vcc is off). figure 8.1 shows the gp i/o port's structure. right after power - on reset, those ports default to perform basic input function except ports in gp3 and gp4 which maintain their previous settings until a battery loss condition. table 8.1 selection bit 0 = output 1 = input inversion bit 0 = non inverse 1 = inv erse basic i/o operations 0 0 basic non - inverting output 0 1 basic inverting output 1 0 basic non - inverting input 1 1 basic inverting input
W83627SF preliminary publication release date: nov. 2000 - 86 - revision 0.60 table 8.2 gp i/o port data register register bit assignment gp i/o port bit 0 gp10 bit 1 gp11 bit 2 gp1 2 bit 3 gp13 gp1 bit 4 gp14 bit 5 gp15 bit 6 gp16 bit 7 gp17 bit 0 gp20 bit 1 gp21 gp2 bit 2 gp22 bit 3 gp23 bit 4 gp24 bit 5 gp25 bit 6 gp26 bit 7 gp27 bit 0 gp30 bit 1 gp31 gp3 bit 2 gp32 bit 3 gp33 bit 4 gp34 bit 5 gp3 5 bit 0 gp40 gp4 bit 1 gp41 bit 2 gp42
W83627SF preliminary publication release date: nov. 2000 - 87 - revision 0.60 table 8.2, continued gp i/o port data register register bit assignment gp i/o port bit 0 gp50 bit 1 gp51 bit 2 gp52 bit 3 gp53 gp5 bit 4 gp54 bit 5 gp55 bit 6 gp56 bit 7 gp57 bit 0 gp60 bit 1 gp61 gp6 bit 2 gp62 bit 3 gp63 bit 0 gp70 bit 1 gp71 gp7 bit 2 gp72 bit 3 gp73 bit 4 gp74
W83627SF preliminary publication release date: nov. 2000 - 88 - revision 0.60 figure 8.1
W83627SF preliminary publication release date: nov. 2000 - 89 - revision 0.60 9. plug and play config uration the W83627SF uses compatible pnp protocol to access configuration registers for setting up different types of configurations. in W83627SF, there are twelve logical devices (from logical device 0 to logical device c with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: fdc (logical de vice 0), prt (logical device 1), uart a (logical device 2), uart b (logical device 3), kbc (logical device 5), cir (consumer ir, logical device 6), gp1 (logical device 7), gp2 (logical device 8), gp3 and gp4 (logical device 9), acpi ((logical device a), sm art card interface (logical device b), and gp5, gp6, and gp7 (logical device c). each logical device has its own configuration registers (above cr30). host can access those registers by writing an appropriate logical device number into logical device sel ect register at cr07. 9.1 compatible pnp 9.1.1 extended function registers in compatible pnp, there are two ways to enter extended function and read or write the configuration registers. hefras (cr26 bit 6) can be used to select one out of these two methods of entering the extended function mode as follows: hefras address and value 0 write 87h to the location 2eh twice 1 write 87h to the location 4eh twice after power - on reset, the value on rtsa# (pin 43) is latched by hefras of cr26. in compatible pnp, a specific value (87h) must be written twice to the extended functions enable register (i/o port address 2eh or 4eh). secondly, an index value (02h, 07h - ffh) must be written to the extended functions index register (i/o port address 2eh or 4eh same as extended functions enable register) to identify which
W83627SF preliminary publication release date: nov. 2000 - 90 - revision 0.60 configuration register is to be accessed. the designer can then access the desired configuration register through the extended functions data register (i/o port address 2fh o r 4fh). after programming of the configuration register is finished, an additional value (aah) should be written to efers to exit the extended function mode to prevent unintentional access to those configuration registers. the designer can also set bit 5 of cr26 (lockreg) to high to protect the configuration registers against accidental accesses. the configuration registers can be reset to their default or hardware settings only by a cold reset (pin mr = 1). a warm reset will not affect the configuration registers. 9.1.2 extended functions enable registers (efers) after a power - on reset, the W83627SF enters the default operating mode. before the W83627SF enters the extended function mode, a specific value must be programmed into the extended function enable re gister (efer) so that the extended function register can be accessed. the extended function enable registers are write - only registers. on a pc/at system, their port addresses are 2eh or 4eh (as described in previous section). 9.1.3 extended function index regi sters (efirs), extended function data registers(efdrs) after the extended function mode is entered, the extended function index register (efir) must be loaded with an index value (02h, 07h - feh) to access configuration register 0 (cr0), configuration regist er 7 (cr07) to configuration register fe (crfe), and so forth through the extended function data register (efdr). the efirs are write - only registers with port address 2eh or 4eh (as described in section 12.2.1) on pc/at systems; the efdrs are read/write r egisters with port address 2fh or 4fh (as described in section 9.2.1) on pc/at systems. 9.2 configuration sequence to program W83627SF configuration registers, the following configuration sequence must be followed: (1). enter the extended function mode (2). configure the configuration registers (3). exit the extended function mode 9.2.1 enter the extended function mode to place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to extended function enable registers(efers, i.e. 2eh or 4eh).
W83627SF preliminary publication release date: nov. 2000 - 91 - revision 0.60 9.2.2 configurate the configuration registers the chip selects the logical device and activates the desired logical devices through extended function index register(efir) and extended function data register(efdr). efir is located at the same addres s as efer, and efdr is located at address (efir+1). first, write the logical device number (i.e.,0x07) to the efir and then write the number of the desired logical device to the efdr. if accessing the chip(global) control registers, this step is not requir ed. secondly, write the address of the desired configuration register within the logical device to the efir and then write (or read) the desired configuration register through efdr. 9.2.3 exit the extended function mode to exit the extended function mode, one w rite of 0xaa to efer is required. once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. 9.2.4 software programming example the following example is written in intel 8086 assembly language. it assumes that the efer is located at 2eh, so efir is located at 2eh and efdr is located at 2fh. if hefras (cr26 bit 6) is set, 4eh can be directly replaced by 4eh and 2fh replaced by 4fh. ; --------------------------------------------------------------- -------------------- ; enter the extended function mode ,interruptible double - write | ; ----------------------------------------------------------------------------------- mov dx,2eh mov al,87h out dx,al out dx,al ; ------------------------------------- ---------------------------------------- ; configurate logical device 1, configuration register crf0 | ; ----------------------------------------------------------------------------- mov dx,2eh mov al,07h out dx,al ; point to logical device number reg. m ov dx,2fh
W83627SF preliminary publication release date: nov. 2000 - 92 - revision 0.60 mov al,01h out dx,al ; select logical device 1 ; mov dx,2eh mov al,f0h out dx,al ; select crf0 mov dx,2fh mov al,3ch out dx,al ; update crf0 with value 3ch ; ------------------------------------------ ; exit extended function mode | ; ----- ------------------------------------- mov dx,2eh mov al,aah out dx,al
W83627SF preliminary public ation release date: nov. 2000 - 93 - revision 0.60 10. acpi registers featu res W83627SF supports both acpi and legacy power managements. the switch logic of the power management block generates an smi# interrupt in the legacy mode and an pme# interrupt in the acpi mode. the new acpi feature routes smi# / pme# logic output either to smi# or to pme# .the smi# / pme# logic routes to smi# only when both pme_en = 0 and smipme_oe = 1. similarly, the smi# / pme# logic routes to pme# only when both pme_en = 1 and smipme_oe = 1. device idle timers device trap timer sleep/wake state machine wak_sts clock control pme smi global stby irqs logic irq events pme_en smipme_oe pme smi / 0 1 smipme_oe
W83627SF preliminary public ation release date: nov. 2000 - 94 - revision 0.60 11. smart card interface because of si milarity of transmission protocol to uart, the register map of smart card interface of winbond i/o is designed to be uart - like for easy programming. details of these registers are described as follows. 11.1 receiver buffer register (rbr, read only at "base add ress + 0" when bdlab = 0) data from ic card are buffered in this register for host to read. 11.2 transmitter buffer register (tbr, write only at "base address + 0" when bdlab = 0) host writes to this register to send data to ic card. 11.3 interrupt control regis ter (icr, at "base address + 1" when bdlab = 0) this 8 - bit register allows the four types of interrupts. the interrupt system can be completely disabled by resetting bits 0 through 4 of the interrupt control register (icr). a selected interrupt can be e nabled by setting the appropriate bits of this register to a logical 1. enable rbr data ready interrupt (erdri) enable tbr empty interrupt (etbrei) enable ssr interrupt (essri) enabel scpsnt interrupt (escpti) 7 6 5 4 3 2 1 0 0 0 0 0 bit 7 - 5: these bits are always logic 0. bit 4: escpti. setting this bit to a logical 1 enables scpsnt interrupt when a card is inserted. bit 3: this bit is al ways logic 0. bit 2: essri. setting this bit to a logical 1 enables smart card interface status register interrupt. bit 1: etbrei. setting this bit to a logical 1 enables tbr empty interrupt. bit 0: erdri. setting this bit to a logical 1 enables rbr d ata ready interrupt.
W83627SF preliminary public ation release date: nov. 2000 - 95 - revision 0.60 11.4 interrupt status register (isr, read only at "base address + 2") this register reflects the smart card interface interrupt status, which is encoded by different interrupt sources into 4 bits. no interrupt pending interrupt status bit 0 interrupt status bit 0 interrupt status bit 0 scpsnt toggle interrupt (scpti) scpsnt line status fifo enabled fifo enabled 7 6 5 4 3 2 1 0 bit 7, 6: the se two bits are set to a logical 1 when sfr bit 0 = 1. bit 5: reflect value of scpsnt line status. bit 4: set to 1 if scpsnt toggles when this type of interrupt is enabled. bit 0 of this register is also set to 0 if this type of interrupt occurs. bit 3 - 1: these three bits identify the priority level of the pending interrupt, as shown in the table below. bit 0: this bit is a logical 1 if there is no interrupt pending. if one of the interrupt sources has occurred, this bit will be set to a logical 0. i nterrupt control function isr interrupt set and fu nction bit 3 bit 2 bit 1 bit 0 interrupt priority interrupt type interrupt source clear interrupt 0 0 0 1 - - no interrupt pending - 0 1 1 0 first smart card interface receive status 1. oer = 1 2. pber =1 3. nser = 1 4. sbd = 1 read scsr 0 1 0 0 second rbr data ready 1. rbr data ready 2. fifo interrupt active level reached 1. read rbr 2. read rbr until fifo data under active level 1 1 0 0 second fifo data timeout data prese nt in rx fifo for 4 characters period of time since last access of rx fifo. read rbr 0 0 1 0 third tbr empty tbr empty 1. write data into tbr 2. read isr (if priority is third)
W83627SF preliminary public ation release date: nov. 2000 - 96 - revision 0.60 11.5 smart card fifo control register (scfr, write only at "base address + 2") this register is used to control the fifo functions of smart card interface. fifo enable receiver fifo reset transmitter fifo reset rx interrupt active level (lsb) rx interrupt active level (msb) 7 6 5 4 3 2 1 0 bit 6, 7: these two bits are used to set the active level for the receiver fifo interrupt. for example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver fifo, the interrupt will be activated to notify the cpu to read the data from the fifo. fifo trigger level bit 7 bit 6 rx fifo interrupt ac tive level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 bit 5 - 3: reserved. bit 2: setting this bit to a logical 1 resets the tx fifo counter logic to initial state. this bit will be cleared to a logical 0 by itself after being set to a logical 1. bit 1: setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will be cleared to a logical 0 by itself after being set to a logical 1. bit 0: this bit enables fifo of smart card interface. this bit should be set to a logical 1 before other bits of scfr are programmed.
W83627SF preliminary public ation release date: nov. 2000 - 97 - revision 0.60 11.6 smar t card control register (sccr, write only at "base address + 3") the smart card control register controls and defines the parity bit protocol for asynchronous data communications. parity bit enable (pbe) even parity enable (epe) baud rate divisor latch access bit (bdlab) 7 6 5 4 3 2 1 0 0 0 0 1 1 bit 7: bdlab. when this bit is set to a logical 1 , designers can access the divisor (in 16 - bit binary format) from the divisor latches of the baudrate generator during a read or write operation. when this bit is reset, the receiver buffer register, the transmitter buffer register, or the interrupt contro l register can be accessed. bit 6 - 5: reserved. always 0 when read. bit 4: epe. this bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. when this bit is set, an even number of logic 1's are sent o r checked. when the bit is reset, an odd number of logic 1's are sent or checked. bit 3: pbe. when this bit is set, the position between the last data bit and the stop bit of the sout will be stuffed with the parity bit at the transmitter. for the recei ver, the parity bit in the same position as the transmitter will be detected. bit 2 ? 0: reserved. bit 2 is always 0 and bit 1 ? 0 are always 1 when read. 11.7 interrupt enable register (ier, at "base address + 4") this register contains global interrupt ena ble bit of smart card interface. irq enable 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 bit 7 - 4: reserved. always 0 when read. bit 3: the smart card interface interrupt output is enabled by setting this bit to a logic 1. bit 2 ? 0: reserved. always 0 when read.
W83627SF preliminary public ation release date: nov. 2000 - 98 - revision 0.60 11.8 smart card status register (scsr, at "base address + 5") this 8 - bit register provides information about the status of the data transfer during communication. rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) transmitter buffer register empty (tbre) transmitter shift register empty (tsre ) rx fifo error indication (rfei) 7 6 5 4 3 2 1 0 bit 7: rfei. this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the fifo. it is cleared by reading scsr until there are no remaining errors left in the fifo. bit 6: tsre. if the transmitting fifo and tsr are both empty, it will be set to a logical 1. otherwise, this bit will be reset to a logical 0. bit 5: tbre. when a data character is transferred from tbr to tsr, this bit will be set to a logical 1. if etbrei of icr is a logical 1, an interrupt will be generated to notify the cpu to write the next data. it will be re set to a logical 0 when cpu writes data into tbr or fifo. bit 4: sbd. this bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. when the cpu rea ds scsr, it will clear this bit to a logical 0. bit 3: nser. this bit is set to a logical 1 to indicate that the received data have no stop bit. when cpu reads scsr, it will clear this bit to a logical 0. bit 2: pber. this bit is set to a logical 1 to i ndicate that parity bit of received data is incorrect. when cpu reads scsr, it will clear this bit to a logical 0. bit 1: oer. this bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by cpu. when cpu reads usr, it will clear this bit to a logical 0. bit 0: rdr. this bit is set to a logical 1 to indicate received data are ready to be read by cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0.
W83627SF preliminary public ation release date: nov. 2000 - 99 - revision 0.60 11.9 extended control register (ecr, at "base address + 7") this 8 - bit register provides control settings for smart card interface. warm reset scio direction clkstp clkstph scclk frequency select bit 0 scclk frequency select bit 1 internal sampling clock base select bit 0 internal sampling clock base select bit 1 7 6 5 4 3 2 1 0 bit 7 ? 6: these two bits (basesel1 and basesel0 respectively) select internal sampling cl ock base multiplier versus baud rate. basesel1 , basesel0 multiplier 00 14x 01 16x 10 18x 11 16x bit 5 ? 4: these two bits (clksel1 and clksel0 respectively) select frequency of scclk. clksel1, clksel0 scclk frequuency 00 1.5 mhz 01 3 mhz 10 6 mhz 11 12 mhz bit 3: clkstph. this bit determines scclk stuck at high or low after clkstp is set to 1. scclk stays high if clkstph is equal to 1 and stays low otherwise. bit 2: clkstp. setting this bit to 1 will stop scclk. bit 1: scdir. this bit dete rmine direction of scio pin. scio serves as an input port if scdir is 1. it is an output port if scdir is 0. bit 0: wrst. writing a 1 to this bit issues a warm reset to ic card. it is self - cleared after writing a 1.
W83627SF preliminary public ation release date: nov. 2000 - 100 - revision 0.60 11.10 baud rate divisor latch high and ba ud rate divisor latch low (bhl and bll at "base address + 1" and "base address + 0" respectively when bdlab = 1) combining with basesel1 and basesel0 of ecr, these two bytes of registers provide user all the possible combinations to cover all the availab le settings regarding clock rate conversion factor and baud rate adjustment factor.
W83627SF preliminary public ation release date: nov. 2000 - 101 - revision 0.60 smart card interface register bit map. b it n umber r egister a ddress b ase 0 1 2 3 4 5 6 7 + 0 bdlab = 0 r eceiver b uffer r egister (read only) rbr rx data bit 0 rx data bit 1 rx data bit 2 rx data bit 3 rx data bit 4 rx data bit 5 rx data bit 6 rx data bit 7 + 0 bdlab = 0 t ransmitter b uffer r egister ( write only) tbr tx data bit 0 tx data bit 1 tx data bit 2 tx data bit 3 tx data bit 4 tx data bit 5 tx data bit 6 tx data bit 7 + 1 bdlab = 0 i nterrupt c ontrol r egister icr rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) ssr interrupt enable (eusri) 0 scpsnt toggle interrupt enable (escpti) 0 0 0 + 2 i nterrupt s tatus r egiste r ( read only ) isr "0" if interrupt pending interrupt status bit (0) interrupt status bit (1) interrupt status bit (2) scpsnt toggle interrupt status (scpti) scpsnt line status fifos enabled ** fifos enabled ** + 2 smart card fifo c ontrol r egister (write only) scfr fifo enable rcvr fifo reset xmit fifo reset reserved reserved reversed rx interrupt active level (lsb) rx interrupt active level (msb) + 3 smart card c ontrol r egister sccr 1 1 0 parity bit enable (pbe) even parity enable (epe) 0 0 baudrate div isor latch access bit (bdlab) + 4 interrupt enable register ier 0 0 0 irq enable 0 0 0 0 + 5 smart card s tatus r egister scsr rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) tbr empty ( tbre) tsr empty (tsre) rx fifo error indication (rfei) + 6 reserved + 7 extended control register ecr warm reset scio direction clkstp clkstph scclk frequency select 0 scclk frequency select 1 internal sampling clock base select 0 internal sampl ing clock base select 1 + 0 bdlab = 1 b audrate d ivisor l atch l ow bll bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 + 1 bdlab = 1 b audrate d ivisor l atch h igh bhl bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
W83627SF preliminary public ation release date: nov. 2000 - 102 - revision 0.60 12. serial irq W83627SF supports a se rial irq scheme. this allow a signal line to be used to report the legacy isa interrupt rerquests. because more than one device may need to share the signal serial irq signal line, an open drain signal scheme is used. the clock source is the pci clock. the serial interrupt is transfered on the irqser signal, one cycle consisting of three frames types: a start frame, several irq/data frame, and one stop frame. 12.1 start frame there are two modes of operation for the irqser start frame: quiet mode and continu ous mode. in the quiet mode, the peripheral drives the serirq signal active low for one clock, and then tri - states it. this brings all the states machines of the peripherals from idle to active states. the host controller will then take over driving irqs er signal low in the next clock and will continue driving the irqser low for programmable 3 to 7 clock periods. this makes the total number of clocks low for 4 to 8 clock periods. after these clocks, the host controller will drive the irqser high for one clock and then tri - states it. in the continuous mode, only the host controller initiates the start frame to update irq/data line information. the host controller drives the irqser signal low for 4 to 8 clock periods. upon a reset, the irqser signal is d efaulted to the continuous mode for the host controller to initiate the first start frame. 12.2 irq/data frame once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. each irq/data fr ame is three clocks long: sample phase, recovery phase, and turn - around phase. during the sample phase, the peripheral drives serirq low if the corresponding irq is active. if the corresponding irq is inactive, then irqser must be left tri - stated. during the recovery phase, the peripheral device drives the irqser high. during the turn - around phase, the peripheral device left the irqser tri - stated. the irq/data frame has a number of specific order, as shown in table 3 - 1.
W83627SF preliminary public ation release date: nov. 2000 - 103 - revision 0.60 table 12 - 2 irqser sampling per iods irq/data frame signal sampled # of clocks past start 1 irq0 2 2 irq1 5 3 smi# 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 17 iochck # 50 18 inta# 53 19 intb# 56 20 intc# 59 21 intd# 62 32:22 unassigned 95 12.3 stop frame after all irq/data frames have completed, the host controller will terminate irqser by a stop frame. only the host controller can initiate the stop frame by driving irqser low for 2 or 3 clocks. if the stop frame is low for 2 clocks, the next irqser cycle's sample mode is the quiet mode. if the stop frame is low for 3 clocks, the next irqser cycle's sample mode is the continuous mode.
W83627SF preliminary publication re lease date: nov . 2000 - 104 - revision 0. 6 0 13. configuration regist er 13.1 chip (global) control register cr02 (default 0x00) bit 7 - 1 : reserved. bit 0 : swrst -- > soft reset. cr07 bit 7 - 0 : ldnb7 - ldnb0 -- > logical device number bit 7 - 0 cr20 bit 7 - 0 : devidb7 - debidb0 -- > device id bit 7 - bit 0 = 0x59 (read only). cr21 bit 7 - 0 : devrevb7 - debrevb0 -- > device rev bit 7 - bit 0 = 0x5v (read only, v is version number). cr22 (default 0xff) bit 7 : reserved. bit 6 : hmpwd. hardware monitor power down enable. = 0 power down = 1 no power down bit 5 : urbpwd. uart b power down enable. = 0 power down = 1 no power down bit 4 : urapwd. uart a power down enable. = 0 power down = 1 no power down bit 3 : prtpwd. printer port power down enable. = 0 power down = 1 no power down bit 2 : reserved. bit 1 : scpwd. smart card interface power down enable. = 0 power down = 1 no power down bit 0 : fdcpwd. fdc power down enable. = 0 power down = 1 no power down
W83627SF preliminary publication re lease date: nov . 2000 - 105 - revision 0. 6 0 cr23 (default 0x00) bit 7 - 1 : reserved. bit 0 : ipd (immediate power down). when set to 1, it will put the whole chip into power down mode immediately. cr24 (default 0b1s000s0s) bit 7 : reserved. bit 6 : clksel = 0 the clock input on pin 1 should be 24 mhz. = 1 the clock input on pin 1 s hould be 48 mhz. the corresponding power - on setting pin is soutb (pin 83). bit 5 - 3 : reserved. bit 2 : enkbc = 0 kbc is disabled after hardware reset. = 1 kbc is enabled after hardware reset. this bit is read only, and set/reset by power - on setting pin. the corresponding power - on setting pin is souta (pin 54). bit 1 : reserved bit 0 : pnpcsv = 0 the compatible pnp address select registers have default values. = 1 the compatible pnp address select registers have no default value. when try ing to make a change to this bit, new value of pnpcvs must be complementary to the old one to make an effective change. for example, the user must set pnpcsv to 0 first and then reset it to 1 to reset these pnp registers if the present value of pnpcsv is 1. the corresponding power - on setting pin is ndtra (pin 52). cr25 (default 0x00) this register contains enable bit for tri - state device's output pins when corresponding power down enable bit (specified in cr24) is set. bit 7 - 6 : reserved bit 5 : urbtri. for uart b device. bit 4 : uratri. for uart a device. bit 3 : prttri. for printer port device. bit 2 : reserved. bit 1 : sctri. for smart card interface. bit 0 : fdctri. for fdc device.
W83627SF preliminary publication re lease date: nov . 2000 - 106 - revision 0. 6 0 cr26 (default 0b0s000000) bit 7 : sel4fdd = 0 select two fdd mode. = 1 select four fdd mode. bit 6 : hefras this bit defines how to enable configuration mode. the corresponding power - on setting pin is nrtsa (pin 51). = 0 write 87h to the location 2eh twice. = 1 write 87h to the location 4eh twice. bit 5 : lockreg = 0 enable r/w configuration registers. = 1 disable r/w configuration registers. bit 4 :reserve bit 3 : dsfdlgrq = 0 enable fdc legacy mode on irq and drq selection, then do register bit 3 is effective on selecting irq. = 1 disable fdc legacy mode on irq and drq selection, then do register bit 3 is not effective on selecting irq. bit 2 : dsprlgrq = 0 enable prt legacy mode on irq and drq selection, then dcr bit 4 is effective on selecting irq. = 1 disable prt legacy mode o n irq and drq selection, then dcr bit 4 is not effective on selecting irq. bit 1 : dsualgrq = 0 enable uart a legacy mode irq selecting, then mcr bit 3 is effective on selecting irq. = 1 disable uart a legacy mode irq selecting, then mcr bit 3 is not effective on selecting irq. bit 0 : dsublgrq = 0 enable uart b legacy mode irq selecting, then mcr bit 3 is effective on selecting irq. = 1 disable uart b legacy mode irq selecting, then mcr bit 3 is not effective on selecting irq.
W83627SF preliminary publication re lease date: nov . 2000 - 107 - revision 0. 6 0 cr28 (default 0x00) bit 7 - 3 : reserved. bit 2 - 0 : prtmods2 - prtmods0 = 0xx parallel port mode = 100 reserved = 101 external fdc mode = 110 reserved = 111 external two fdc mode cr29 (gpio3 multiplexed pin selection register. vbat powered. default 0x00) bit 7 : pin64s = 0 susled (susled control bits are in crf3 of logical device 9) = 1 gp35 bit 6 : pin69s = 00 cirrx# = 01 gp34 bit 5 : pin70s = 0 rsmrst# = 1 gp33 bit 4 : pin71s = 0 pwrok = 1 gp32 bit 3 : pin72s = 0 pwrctl# = 1 gp31 bit 2 : pin 73s = 0 slp_sx# = 1 gp30 bit 1 : reserved. bit 0 : pin103s = 0 pin 103 and pin 104 function as gp41 and gp40 respectively. =1 pin 103 is s5# signal input signal and pin 104 is system s3 state power control signal. the corresponding power on setting pin is gp42 (pin 102). its value is latched on the rising edge of internal rsmrst# signal (delay of rising edge of internal rsmrst# signal from vsb on is half way of that of external rsmrst# pin). the s 3 state power control pin (pin 104) outputs low when vsb is on. it outputs high following the falling edge of slp_sx# (pin 73) signal falling edge. then it is reset by the falling edge of s5# signal (pin 103). *note: the falling edge of pwrctl# signal (pin 72) is delayed an additional 5ms from the falling edge of slp_sx# signal for supporting str (suspend to ram) function.
W83627SF preliminary publication re lease date: nov . 2000 - 108 - revision 0. 6 0 cr2a (gpio multiplexed pin selection register 1. vcc powered. default 0x7c) bit 7 : port select (select game port or general p urpose i/o port 1) = 0 game port = 1 enable bit 6 - 2 selection between gp10 ~ gp14 or 8042 kbc p12 - p16 for pin 128 - 124. bit 6 : pin128s = 0 8042 p12 = 1 gp10 bit 5 : pin127s = 0 8042 p13 = 1 gp11 bit 4 : pin126s = 0 8042 p14 = 1 gp12 bit 3 : pin125s = 0 8042 p15 = 1 gp13 bit 2 : pin124s = 0 8042 p16 = 1 gp14 bit 1 : pin120s = 0 mso (midi serial data output) = 1 irqin0 (select irq resource through crf3 bit 3 - 0 of logical device 8) bit 0 : pin119s = 0 msi (midi serial data input) = 1 g p20 cr2b (gpio multiplexed pin selection register 2. vcc powered. default 0xc0) bit 7 - 6 : reserved bit 5 : pin90s = 0 pled (pled0 control bits are in crf5 bit 7 - 6 of logical device 8) = 1 gp23 bit 4 : pin89s = 0 wdto (watch dog timer is controlled by crf5, crf6, crf7 of logical device 8) = 1 gp24
W83627SF preliminary publication re lease date: nov . 2000 - 109 - revision 0. 6 0 bit 3 : pin88s = 0 irrx = 1 gp25 bit 2 : pin87s = 0 irtx = 1 gp26 bit 1 - 0 :pin2s = 00 drvden1 = 01 smi# = 10 irqin1 (select irq resource through crf3 bit 7 - 4 of logical device 8) = 11 gp 27 cr2c (gpio multiplexed pin selection register 3. vcc powered. default 0bsss11111) bit 7 : multi - function selection bit for pin 91, 92, 98 ? 100, and 106 ? 110. = 0 gp21 ? 22, gp60 ? 62, and gp51 - gp55 = 1 vid function the corresponding power on setting pin is gp57 (pin 102). its value is latched on the rising edge of pwrok after vdd is on. refer to crf9and crfa of logical device c for detailed description of vid function. bit 6 - 5 : multi - function selection bit for pin 112, 113, 115, 116, and 1 18 = 00 gp74 - 71 and gp70 = 01 reserved = 10 smart card function = 11 reserved the corresponding power on setting pin for bit 6 is gp70 (pin 118) and gp72 (pin 115) for bit5. both values are latched on the rising edge of pwrok after vdd is on. if either bit 5or bit 6 is set to "1" after pwrok rising edge, these two bit can only be read. they can be written if powered on to select gp function initially and switch to smard card function. bit 4 - 0 : reserved cr2d (default 0x00) test mode: reserved for winbond. cr2e (default 0x00) test mode: reserved for winbond. cr2f (default 0x00) test mode: reserved for winbond.
W83627SF preliminary publication re lease date: nov . 2000 - 110 - revision 0. 6 0 13.2 logical device 0 (fdc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf0 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select fdc i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x06 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resource for fdc. cr74 (default 0x02 if pnpcsv = 0 during por, default 0x04 otherwise) bit 7 - 3 : reserved. bit 2 - 0 : these bits select drq resource for fdc. = 0x00 dma0 = 0x01 dma1 = 0x02 dma2 = 0x03 dma3 = 0x04 - 0x07 no dma active crf0 (default 0x0e) fdd mode register bit 7 : fipurdwn this bit controls the internal pull - up resistors of the fdc input pins rdata, index, trak0, dskc hg, and wp. = 0 the internal pull - up resistors of fdc are turned on.(default) = 1 the internal pull - up resistors of fdc are turned off. bit 6 : intvertz this bit determines the polarity of all fdd interface signals. = 0 fdd interface signals are active low. = 1 fdd interface signals are active high.
W83627SF preliminary publication re lease date: nov . 2000 - 111 - revision 0. 6 0 bit 5 : drv2en (ps2 mode only) when this bit is a logic 0, indicates a second drive is installed and is reflected in status register a. bit 4 : swap drive 0, 1 mode = 0 no swap (defau lt) = 1 drive and motor sel 0 and 1 are swapped. bit 3 - 2 :interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30 bit 1 : fdc dma mode = 0 burst mode is enabled = 1 non - burst mode (default) bit 0 : floppy mode = 0 normal floppy mode (default) = 1 enhanced 3 - mode fdd crf1 (default 0x00) bit 7 - 6 : boot floppy = 00 fdd a = 01 fdd b = 10 fdd c = 11 fdd d bit 5, 4 : media id1, media id0. these bits will be reflected on fdc's tape dri ve register bit 7, 6. bit 3 - 2 : density select = 00 normal (default) = 01 normal = 10 1 ( forced to logic 1) = 11 0 ( forced to logic 0) bit 1 : disfddwr = 0 enable fdd write. = 1 disable fdd write(forces pins we, wd stay high). bit 0 : swwp = 0 normal, use wp to determine whether the fdd is write protected or not. = 1 fdd is always write - protected.
W83627SF preliminary publication re lease date: nov . 2000 - 112 - revision 0. 6 0 crf2 (default 0xff) bit 7 - 6 : fdd d drive type bit 5 - 4 : fdd c drive type bit 3 - 2 : fdd b drive type bit 1 - 0 : fdd a drive type crf4 (default 0x00) fdd0 selection: bit 7 : reserved. bit 6 : precomp. disable. = 1 disable fdc precompensation. = 0 enable fdc precompensation. bit 5 : reserved. bit 4 - 3 : drts1, drts0: data rate table select (refer to table a). = 00 select regular drives and 2.88 format = 01 3 - mode drive = 10 2 meg tape = 11 reserved bit 2 : reserved. bit 1:0 : dtype0, dtype1: drive type select (refer to table b). crf5 (default 0x00) fdd1 selection: same as fdd0 of crf4.
W83627SF preliminary publication re lease date: nov . 2000 - 113 - revision 0. 6 0 table a drive rate table select data rate selected data rate selden drts1 drts0 drate1 drate0 mfm fm 1 1 1meg --- 1 0 0 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 1 1 1meg --- 1 0 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 1 1 1meg --- 1 1 0 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 table b dtype0 dtype1 drvden0(pin 2) drvden1(pin 3) drive type 0 0 selden drate0 4/2/1 mb 3.5 ? ? 2/1 mb 5.25 ? 2/1.6/1 mb 3.5 ? (3 - mode) 0 1 drate1 drate0 1 0 selden drate0 1 1 drate0 drate1
W83627SF preliminary publication re lease date: nov . 2000 - 114 - revision 0. 6 0 13.3 logical device 1 (parallel port) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0x78 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select parallel port i/o base address. [0x100:0xffc] on 4 byte boundary (epp not supported) or [0x100:0xff8] on 8 byte boundary (all modes support ed, epp is only available when the base address is on 8 byte boundary). cr70 (default 0x07 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for parallel port. cr74 (default 0x03) bit 7 - 3 : reserved. bit 2 - 0 : these bits select drq resource for parallel port. 0x00=dma0 0x01=dma1 0x02=dma2 0x03=dma3 0x04 - 0x07= no dma active crf0 (default 0x3f) bit 7 : reserved. bit 6 - 3 : ecp fifo threshold. bit 2 - 0 : parallel port mode (cr28 prtmods2 = 0) = 100 printer mode (default) = 000 standard and bi - direction (spp) mode = 001 epp - 1.9 and spp mode = 101 epp - 1.7 and spp mode = 010 ecp mode = 011 ecp and epp - 1.9 mode = 111 ecp and epp - 1.7 mode.
W83627SF preliminary publication re lease date: nov . 2000 - 115 - revision 0. 6 0 13.4 logical device 2 (uart a) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 : = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf8 if pnpcsv = 0 dur ing por, default 0x00, 0x00 otherwise) these two registers select serial port 1 i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x04 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resource for serial port 1. crf0 (default 0x00) bit 7 - 2 : reserved. bit 1 - 0 : suaclkb1, suaclkb0 = 00 uart a clock source is 1.8462 mhz (24mhz/13) = 01 uart a clock source is 2 mhz (24mhz/12) = 10 uart a clock source is 24 mhz (24 mhz/1) = 11 uart a clock source is 14.769 mhz (24mhz/1.625) 13.5 logical device 3 (uart b) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x02, 0xf8 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select serial port 2 i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x03 if pnpcsv = 0 during por, default 0x00 otherwis e) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for serial port 2.
W83627SF preliminary publication re lease date: nov . 2000 - 116 - revision 0. 6 0 crf0 (default 0x00) bit 7 - 4 : reserved. bit 3 : rxw4c = 0 no reception delay when sir is changed from tx mode to rx mode. = 1 reception delays 4 characters - time (40 bit - time) when sir is changed from tx mode to rx mode. bit 2 : txw4c = 0 no transmission delay when sir is changed from rx mode to tx mode. = 1 transmission delays 4 characters - time (40 bit - time) when sir is changed from rx mode to tx mode. bit 1 - 0 : subclkb1, subclkb0 = 00 uart b clock source is 1.8462 mhz (24mhz/13) = 01 uart b clock source is 2 mhz (24mhz/12) = 10 uart b clock source is 24 mhz (24mhz/1) = 11 uart b clock source is 14.769 mhz (24mhz/1.625) crf1 (default 0x00) bit 7 : reserved. bit 6 : irlocsel. ir i/o pins' location select. = 0 through sinb/soutb. = 1 through irrx/irtx. bit 5 : irmode2. ir function mode selection bit 2. bit 4 : irmode1. ir function mode selection bit 1. bit 3 : i rmode0. ir function mode selection bit 0. ir mode ir function irtx irrx 00x disable tri - state high 010* irda active pulse 1.6 m s demodulation into sinb/irrx 011* irda active pulse 3/16 bit time demodulation into sinb/irrx 100 ask - ir inverting irtx/soutb pin routed to sinb/irrx 101 ask - ir inverting irtx/soutb & 500 khz clock routed to sinb/irrx 110 ask - ir inverting irtx/soutb demodulation into sinb/irrx 111* ask - ir inverting irtx/soutb & 500 khz clock demodulation into sinb/irrx note: the notation is normal mode in the ir function.
W83627SF preliminary publication re lease date: nov . 2000 - 117 - revision 0. 6 0 bit 2 : hduplx. ir half/full duplex function select. = 0 the ir function is full duplex. = 1 the ir function is half duplex. bit 1 : tx2inv. = 0 the soutb pin of uart b function or irtx pin of ir function in normal condition. = 1 inverse the soutb pin of uart b function or irtx pin of ir function. bit 0 : rx2inv. = 0 the sinb pin of uart b function or irrx pin of ir function in normal condition. = 1 inverse the sinb pin of uart b function or irrx pin of ir func tion 13.6 logical device 5 (kbc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x60 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the first kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x00, 0x64 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the second kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr70 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] these bits select irq resource for kint (keyboard). cr72 (default 0x0c if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] these bits select irq resource for mint (ps2 mouse)
W83627SF preliminary publication re lease date: nov . 2000 - 118 - revision 0. 6 0 crf0 (default 0x80) bit 7 - 6 : kbc clock rate selection = 00 select 6mhz as kbc clock input. = 01 select 8mhz as kbc clock input. = 1 0 select 12mhz as kbc clock input. = 11 select 16mhz as kbc clock input. (W83627SF/w83627hf/f - aw can support these 4 kinds of clock input, but W83627SF/ w83627hf/f - pw only support 12mhz clock input) bit 5 - 3 : reserved. bit 2 = 0 port 92 disable. = 1 port 92 enable. bit 1 = 0 gate20 software control. = 1 gate20 hardware speed up. bit 0 = 0 kbrst software control. = 1 kbrst hardware speed up. 13.7 logical device 6 (cir) cr30 (default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activates the l ogical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x00) these two registers select cir i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x00) bit 7 - 4 : reserved. bit [3:0] these bits select irq resource for cir.
W83627SF preliminary publication re lease date: nov . 2000 - 119 - revision 0. 6 0 13.8 logical device 7 (game port and midi port and gpio port 1) cr30 (default 0x00) bit 7 - 3 : reserved. bit 2 = 1 activate midi port. = 0 midi port is disabled if bit 0 is also 0. bit 1 = 1 activate game port. = 0 game port is is disab led if bit 0 is also 0. bit 0 = 1 activate both game port and midi port. = 0 game port is disabled is bit1 is also 0. midi port is disabled if bit2 is also 0. cr60, cr 61 (default 0x02, 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the game port base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x03, 0x30 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the midi port base address [0x100:0xfff] on 2 byt e boundary. cr70 (default 0x09 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for midi port . crf0 (gp10 - gp17 i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp10 - gp17 data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp10 - gp17 inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register.
W83627SF preliminary publication re lease date: nov . 2000 - 120 - revision 0. 6 0 crf3 (midi fifo threshold register. default 0x00) bit 7 - 6: midi fifo threshold. bit 7 bit 6 rx fifo interrupt ac tive level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 bit 5 - 0: reserved 13.9 logical device 8 (gpio port 2) cr30 (gp20 - gp27 default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activate gpio2. = 0 gpio2 is inactive. note: bit 0 is initialized to power on setting value of pin 81 on the rising edge of pwrok. cr60, cr 61 (default 0x00, 0x00) these two registers select gp2 i/o base address [0x100:0xff8] on 1 byte boundary. crf0 (gp20 - gp27 i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp20 - gp27 data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp20 - gp27 inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf3 (default 0x00) bit 7 - 4 : these bits select irq resource for irqin1. b it 3 - 0 : these bits select irq resource for irqin0. crf4 (reserved)
W83627SF preliminary publication re lease date: nov . 2000 - 121 - revision 0. 6 0 crf5 (pled mode register. default 0x00) bit 7 - 6 : select pled mode = 00 power led pin is tri - stated. = 01 power led pin is drived low. = 10 power led pin is a 1hz toggle pulse with 50 duty cycle. = 11 power led pin is a 1/4hz toggle pulse with 50 duty cycle. bit 5 - 4 : reserved bit 3 : select wdto count mode. = 0 second = 1 minute bit 2 : enable the rising edge of keyboard reset(p20) to force time - out event . = 0 disable = 1 enable bit 1 : enable the keyboard reset output low pluse when time - out. = 0 disable = 1 enable bit 0 : reserved crf6 (default 0x00 if engmto is 0, 0x0a if engmto is 1) watch dog timer time - out value. writing a non - zero value to this register causes the counter to load the value to watch dog counter and start counting down. if the bit 7 and bit 6 are set, any mouse interrupt or keyboard interrupt event will also cause the reload of previously - loaded non - zero value to wa tch dog counter and start counting down. reading this register returns current value in watch dog counter instead of watch dog timer time - out value. bit 7 - 0 = 0x00 time - out disable = 0x01 time - out occurs after 1 second/minute = 0x02 time - out occurs after 2 second/minutes = 0x03 time - out occurs after 3 second/minutes ................................................ = 0xff time - out occurs after 255 second/minutes note: the corresponding power on setting pin is pin 81 and its value is latched on the risin g edge of pwrok. 1: crf6 is initialized to be 0x0a and cr30 of this logical device is initialized to be 0x01. 0: crf6 is initialized to be 0x00 and cr30 of this logical device is initialized to be 0x00.
W83627SF preliminary publication re lease date: nov . 2000 - 122 - revision 0. 6 0 crf7 (default 0x00) bit 7 : mouse interrupt reset enable or disable = 1 watch dog timer is reset upon a mouse interrupt = 0 watch dog timer is not affected by mouse interrupt bit 6 : keyboard interrupt reset enable or disable = 1 watch dog timer is reset upon a keyboard interrupt = 0 watch dog time r is not affected by keyboard interrupt bit 5 : force watch dog timer time - out, write only* = 1 force watch dog timer time - out event; this bit is self - clearing. bit 4 : watch dog timer status, r/w = 1 watch dog timer time - out occurred. = 0 watch dog timer counting bit 3 - 0 : these bits select irq resource for watch dog. setting of 2 selects smi. 13.10 logical device 9 (gpio port 3,4 are powered by standby source vsb) cr30 (default 0x02) bit 7 - 1 : reserved. bit 1 = 1 activate gp4. = 0 gp4 is ina ctive. bit 0 = 1 activate gpio3. = 0 gpio3 is inactive. cr60, cr 61 (default 0x02, 0x90 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the gp3, gp4 port base address [0x100:0xfff] on 2 byte boundary. gp3 is accessible through "base address" and gp4 is accessible through "base address" +1. crf0 (gp30 - gp35 i/o selection register. default 0xff bit 7 - 6: reserved) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', resp ective gpio port is programmed as an output port. crf1 (gp30 - gp35 data register. default 0x00 bit 7 - 6: reserved) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp30 - gp35 inversion register. default 0x00 bit 7 - 6: reserved) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data r egister.
W83627SF preliminary publication re lease date: nov . 2000 - 123 - revision 0. 6 0 crf3 (susled mode register. default 0x00) bit 7 - 6 : select suspend led mode = 00 suspend led pin is drived low. = 01 suspend led pin is tri - stated. = 10 suspend led pin is a 1 hz toggle pulse with 50 duty cycle. = 11 suspend led pin is a ? hz toggle pulse with 50 duty cycle. bit 5 - 0 : reserved. crf4 (gp40 - gp42 i/o selection register. default 0x00 bit 7 - 3: reserved) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio p ort is programmed as an output port. crf5 (gp40 - gp42 data register. default 0x00 bit 7 - 3: reserved) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf6 (gp40 - gp42 inversion register. default 0x00 bit 7 - 3: reserved) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. 13.11 lo gical device a (acpi) cr30 (default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr70 (default 0x00) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resources for pme .
W83627SF preliminary publication re lease date: nov . 2000 - 124 - revision 0. 6 0 cre0 (default 0x00) bit 7 : dis - pansw_in. disable panel switch input to turn system power supply on. = 0 pansw_in is wire - anded and connected to pansw_out. = 1 pansw_in is blocked and can not affect pansw_out. bit 6 : enkbwakeup. enable keyboa rd to wake up system through pansw_out. = 0 disable keyboard wake - up function. = 1 enable keyboard wake - up function. bit 5 : enmswakeup. enable mouse to wake - up system via pansw_out. = 0 disable mouse wake - up function. = 1 enable mouse wake - up function. bit 4 : msrkey. select mouse left/right button to wake - up system via pansw_out. = 0 select click on mouse left - button twice to wake the system up. = 1 select click on mouse right - button twice to wake the system up. bit 3 : encirwakeup. enable cir to wake - up system via pansw_out. = 0 disable cir wake - up function. = 1 enable cir wake - up function. bit 2 : kb/ms swap. enable keyboard/mouse port - swap. = 0 keyboard/mouse ports are not swapped. = 1 keyboard/mouse ports are swapped. bit 1 : msxkey. enable any character received from mouse to wake - up the system. = 0 two clicks of mouse left/right - button wakes up the system. = 1 one click of mouse left/right - button wakes up the system. bit 0 : kbxkey. enable any character received from ke yboard to wake - up the system. = 0 only predetermined specific key combination can wake up the system. = 1 any character received from keyboard can wake up the system. cre1 (default 0x00) keyboard wake - up index register this register is used to indicate which keyboard wake - up shift register or predetermined key register is to be read/written via cre2. the first set of wake up key combination is in the range of 0x00 - 0x0e, the second set 0x30 ? 0x3e, and the third set 0x40 ? 0x4e. incoming key combi nation can be read through 0x10 ? 0x1e. the range of cir wake - up index register is in 0x20 - 0x2f. cre2 keyboard wake - up data register this register holds the value of wake - up key register indicated by cre1. this register can be read/written.
W83627SF preliminary publication re lease date: nov . 2000 - 125 - revision 0. 6 0 cre3 (read only. keyboard/mouse wake - up status register) bit 7 ? 6 : reserved. bit 5 : vsbloss: this bit is set when vsb is off. bit 4 : pwrloss_sts: this bit is set when previous power state is off.. bit 3 : cir_sts. the panel switch event is caused by cir wake - up event. this bit is cleared by reading this register. bit 2 : pansw_sts. the panel switch event is caused by pansw_in. this bit is cleared by reading this register. bit 1 : mouse_sts. the panel switch event is caused by mouse wake - up event. this bit is cleared by reading this register. bit 0 : keyboard_sts. the panel switch event is caused by keyboard wake - up event. this bit is cleared by reading this register. cre4 (default 0x00) bit 7 : power loss control bit 2. 0 = d isable acpi resume. 1 = enable acpi resume. bit 6 - 5 : power loss control bit <1:0> 00 = system always turns off when come back from power loss state. 01 = system always turns on when come back from power loss state. 10 = system turns on/off when come back from power loss state depending on the state before power loss. 11 = reserved. bit 4 : suspend clock source select 0 = use internal clock source. 1 = use external suspend clock source(32.768khz). bit 3 : keyboard wake - up type select for wake - up th e system from s1/s2. 0 = password or hot keys programmed in the registers. 1 = any key. bit 2 : enable all wake - up event set in cre0 can wake - up the system from s1/s2 state. this bit is cleared when wake - up event occurs. 0 = disable. 1 = enable. bit 1 - 0 : reserved.
W83627SF preliminary publication re lease date: nov . 2000 - 126 - revision 0. 6 0 cre5 (default 0x00) bit 7 : ens5rst: enable s5# signal (pin 103) to reset susled mode register (crf3 of logical device 9). = 0 susled mode register is reset only by rsmrst#. = 1 susled mode register can be reset by rsmrst# or s5#. bi t 6 - 0 : compared code length. when the compared codes are storaged in the data register, these data length should be written to this register. cre6 (default 0x00) bit 7 : enmdatup: enable an mdat low pulse to wake up system through psout#. = 0 disable. = 1 enable. bit 6 : en_scup: enable scpsnt# of smart card interface to wake up system through psout#. = 0 disable. = 1 enable. bit 5 - 0 : cir baud rate divisor. the clock base of cir is 32k hz, so that the baud rate is 32khz divided by (cir baud r ate divisor + 1). cre7 (default 0x00) bit 7 : enkd3. enable the third set of key combination to wake up system through pansw_out if keyboard wake up function is enabled. = 0 disable the third set of key combination. = 1 enable the third set of key combination. bit 6 : enkd2. enable the second set of key combination to wake up system through pansw_out if keyboard wake up function is enabled. = 0 disable the second set of key combination. = 1 enable the second set of key combination. bit 5 : e nwin98key. enable win98 keyboard dedicated key to wake up system through pansw_out if keyboard wake up function is enabled. = 0 disable win98 keyboard wake up. = 1 enable win98 keyboard wake up. bit 4 : en_onpsout. enable to issue a 0.5 s long psout# pulse when system returns from power loss state and is supposed to be on as described in cre4 bit 6, 5 of logical device a. = 0 disable this function. = 1 enable this function.
W83627SF preliminary publication re lease date: nov . 2000 - 127 - revision 0. 6 0 bit 3 : selwdtorst: select whether watch dog timer function is reset by lre set_l signal or pwrok signal. = 0 watch dog timer function is reset by lreset_l signal. = 1 watch dog timer function is reset by pwrok signal. bit 2 : reset cir power - on function. after using cir power - on, the software should write logical 1 to restart cir power - on function. bit 1 : invert rx data. = 1 inverting rx data. = 0 not inverting rx data. bit 0 : enable demodulation. = 1 enable received signal to demodulate. = 0 disable received signal to demodulate. crf0 (default 0x00) bit 7 : chip pme. chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 6 : cirpme. consumer ir port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 5 : midipme. midi port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 4 : scpme. smart card interface auto power m anagement enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 3 : prtpme. printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 2 : fdcpme. fdc auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 1 : urapme. uart a auto power management enable. = 0 disable the auto power manag ement functions. = 1 enable the auto power management functions. bit 0 : urbpme. uart b auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
W83627SF preliminary publication re lease date: nov . 2000 - 128 - revision 0. 6 0 crf1 (default 0x00) bit 7 : wak_sts. this bit is set when the chip is in the sleeping state and an enabled resume event occurs. upon setting this bit, the sleeping/working state machine will transition the system to the working state. this bit is only set by hardware and is cleared by w riting a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state. bit 6 - 0 : devices' trap status. crf3 (default 0x00) bit 7 - 6 : reserved. return zero when read. bit 5 - 0 : device's irq status. these bits indicate the irq status of the individual device respectively. the device's irq status bit is set by their source device and is cleared by wr iting a 1. writing a 0 has no effect. bit 5 : mouirqsts. mouse irq status. bit 4 : kbcirqsts. kbc irq status. bit 3 : prtirqsts. printer port irq status. bit 2 : fdcirqsts. fdc irq status. bit 1 : urairqsts. uart a irq status. bit 0 : urbirqsts. uart b irq status. crf4 (default 0x00) bit 7 : reserved. return zero when read. bit 4 - 0 : these bits indicate the irq status of the individual gpio function or logical device respectively. the status bit is set by their source function or d evice and is cleared by writing a 1. writing a 0 has no effect. bit 6 : scirqsts. smart card interface irq status. bit 5 : reserved. return zero when read. bit 4 : wdtirqsts. watch dog timer irq status. bit 3 : cirirqsts. consumer ir irq status. bit 2 : midiirqsts. midi irq status. bit 1 : irqin1sts. irqin1 status. bit 0 : irqin0sts. irqin0 status.
W83627SF preliminary publication re lease date: nov . 2000 - 129 - revision 0. 6 0 crf6 (default 0x00) bit 7 - 6 : reserved. return zero when read. bit 5 - 0 : enable bits of the smi / pme generation due to the device's irq. these bits enable the generation of an smi / pme interrupt due to any irq of the devices. smi / pme logic output = (mouirqen and mouirqsts) or (kbcirqen and kbcirqsts) or (prtirqen and prtirqsts) or (fdcirqen and fdcirqsts) or (urairqen and urairqsts) or (urbirqen and urbirqsts) or (scirqen and scirqsts) or (wdtirqen and wdtirqsts) or (irqin3en and irqin3sts) or (irqin2en and irqin2sts) or (i rqin1en and irqin1sts) or (irqin0en and irqin0sts) bit 5 : mouirqen. = 0 disable the generation of an smi / pme interrupt due to mouse's irq. = 1 enable the generation of an smi / pme interrupt due to mouse's irq. bit 4 : kbcirqen. = 0 disable the generation of an smi / pme interrupt due to kbc's irq. = 1 enable the generation of an smi / pme interrupt due to kbc's irq. bit 3 : prtirqen. = 0 disable the generation of an smi / pme interrupt due to printer port's irq. = 1 enable the generation of an smi / pme interrupt due to printer port's irq. bit 2 : fdcirqen. = 0 disable the generation of an smi / pme interrupt due to fdc's irq. = 1 enable the generation of an smi / pme interrupt due to fdc's irq. bit 1 : urairqen. = 0 disable the generation of a n smi / pme interrupt due to uart a's irq. = 1 enable the generation of an smi / pme interrupt due to uart a's irq. bit 0 : urbirqen. = 0 disable the generation of an smi / pme interrupt due to uart b's irq. = 1 enable the generation of an smi / pme interrupt due to uart b's irq.
W83627SF preliminary publication re lease date: nov . 2000 - 130 - revision 0. 6 0 crf7 (default 0x00) bit 7 : reserved. return zero when read. bit 5 - 0 : enable bits of the smi / pme generation due to the gpio irq function or device's irq. bit 6 : scirqen. = 0 disable the generation of an smi / pme interrupt due to smart card interface irq. = 1 enable the generation of an smi / pme interrupt due to smart card interface irq. bit 5 : reserved. return zero when read. bit 4 : wdtirqen. = 0 disable the generation of an smi / pme interrupt due to wat ch dog timer's irq. = 1 enable the generation of an smi / pme interrupt due to watch dog timer's irq. bit 3 : cirirqen. = 0 disable the generation of an smi / pme interrupt due to cir's irq. = 1 enable the generation of an smi / pme interrupt due to cir's irq. bit 2 : midiirqen. = 0 disable the generation of an smi / pme interrupt due to midi's irq. = 1 enable the generation of an smi / pme interrupt due to midi's irq. bit 1 : irqin1en. = 0 disable the generation of an smi / pme interrupt due to irqin1's irq. = 1 enable the generation of an smi / pme interrupt due to irqin1's irq. bit 0 : irqin0en. = 0 disable the generation of an smi / pme interrupt due to irqin0's irq. = 1 enable the generation of an smi / pme interr upt due to irqin0's irq. crf9 (default 0x00) bit 7 - 3: reserved. return zero when read. bit 2 : pme_en: select the power management events to be either an pme or smi interrupt for the irq events. note that: this bit is valid only when smipme_oe = 1. = 0 the power management events will generate an smi event. = 1 the power management events will generate an pme event. bit 1 : fsleep: this bit selects the fast expiry t ime of individual devices. = 0 1 second. = 1 8 milli - seconds. bit 0 : smipme_oe: this is the smi and pme output enable bit. = 0 neither smi nor pme will be generated. only the irq status bit is set. = 1 an smi or pme event will be generated.
W83627SF preliminary publication re lease date: nov . 2000 - 131 - revision 0. 6 0 crfe, ff (default 0x00) reserved for winbond test. 13.12 logical device b (smart card interface) cr30 (default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x00) these two registers select smart card interface base address [0x100:0xfff] on 8 - byte boundary. cr70 (default 0x00) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resource for smart card interface. 13.13 logical device c (gpio port 5,6,7 this power of the ports is source vcc) cr30 (default 0x07) bit 7 - 3 : reserved. bit 2 = 1 activate gp7. = 0 gp7 is inactive. b it 1 = 1 activate gp6. = 0 gp6 is inactive. bit 0 = 1 activate gp5 = 0 gp5 is inactive. cr60, cr 61 (default 0x00) these two registers select the gp5, gp6, gp7 port base address [0x100:0xfff] on 4 byte boundary. gp5 is accessible through "base address", gp6 "base address" +1, and gp7 "base address" +2. crf0 (gp50 - gp56 i/o selection register. default 0x00 bit 7: reserved) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio p ort is programmed as an output port.
W83627SF preliminary publication re lease date: nov . 2000 - 132 - revision 0. 6 0 crf1 (gp50 - gp56 data register. default 0x00 bit 7: reserved) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp50 - gp56 inversion register. default 0x00 bit 7: reserved) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf3 (gp60 - gp63 i/o selection register. default 0xff bit 7 - 4: reserved) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf4 (gp60 - gp63 data register. default 0xff bit 7 - 4: reserved) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf5 (gp60 - gp63 inversion register. default 0x00 bit 7 - 4: reserved) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf6 (gp70 - gp74 i/o selection register. default 0xff bit 7 - 5: reserved) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf7 (gp70 - gp74 data register. default 0xff bit 7 - 5: reserved) if a port is programmed to be an output port, then its respectiv e bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf8 (gp70 - gp74 inversion register. default 0x00 bit 7 - 5: reserved) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf9 (vid input data register. bit 7 - 5: reserved) this register is read only. it contains original vid value. bit 7 ? 5 : reserved. bit 4 ? 0 : original vid value.
W83627SF preliminary publication re lease date: nov . 2000 - 133 - revision 0. 6 0 crfa (vid output data register) this register allows user to configure different vid value. it can be read or written. bit 7 : select vid code tables. = 0 old vid code table. = 1 new vid code table. bit 6 ? 5 : vid guarding bits. the corresponding power on setting pins are gp56, 66 and their values are latched on the rising edge of pwrok signal. bit 6 bit 5 limit 0 0 no constraint 0 1 3 units constraint 1 0 4 units constraint 1 1 5 units constraint bit 4 ? 0 : configurable vid output value. if vidsel of cr2c is 1 (select vid function), gp22, 21, 62 - 60 function as vid inputs and 55 - 51 function as vid outputs. during pwrok = 0, gp55~51 (vidout) are equivalent to gp22, 21, 62~60 (vidin). after power on, user may configure lc.crfa.bit4 - 0 to output a new vidout combination if this new combination comply with the constraints of vid guarding bits specified in bit 6, 5 of this register. vid outputs are equal to vid inputs if constraint is not met.
W83627SF preliminary publication release date: nov . 2000 - 134 - revision 0. 6 0 14. specifications 14.1 absolute maximum ratings parameter rating unit power supply voltage (5v) - 0.5 to 7.0 v input voltage - 0.5 to v dd +0.5 v rtc battery voltage v bat 2.2 to 4.0 v operating temperature 0 to +70 c storage temperature - 55 to +150 c note: e xposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 14.2 dc characteristics (ta = 0 c to 70 c, v dd = 5v 10%, v ss = 0v) parameter sym. min. typ. max. unit conditions rtc battery quiescent current i bat 2.4 ua v bat = 2.5 v acpi stand - by power supply quiescent current i bat 2.0 ma v sb = 5.0 v, all acpi pins are not connected. i/o 8t - ttl level bi - directional pin with source - sink capability of 8 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 8 ma output high voltage v oh 2.4 v i oh = - 8 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v i/o 12t - ttl level bi - directional pin with source - sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih +10 m a v in = v dd input low leakage i l il - 10 m a v in = 0v
W83627SF preliminary publication release date: nov . 2000 - 135 - revision 0. 6 0 14.2 dc characteristics, continued parameter sym. min. typ. max. unit conditions i/o 12tp3 - 3.3 v ttl level bi - directional pin with source - sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih +10 m a v in = 3.3v input low leakage i lil - 10 m a v in = 0v i/od 12t - ttl level bi - directional pin with sink capability of 12 ma and open - dr ain input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 m a v in = 3.3v input low leakage i lil - 10 m a v in = 0v i/o 24t - ttl level bi - directional pin with source - sink capability of 24 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 24 ma output high voltage v oh 2.4 v i oh = - 24 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v out 12t - ttl level output pin with source - sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma out 12tp3 - 3.3 v ttl level output pin with source - sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma od 12 - open - drain output pin with sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma od 24 - open - drain output pin with sink capability of 24 ma output low voltage v ol 0.4 v i ol = 24 ma
W83627SF preliminary publication release date: nov . 2000 - 136 - revision 0. 6 0 14.2 dc characteristics, continued parameter sym. min. typ. max. unit conditions in td - ttl level input pin with internal pull down resistor input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v pull down resistor r 47 k w in t - ttl level input pin input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v in cs - cmos level schmitt - triggered input pin input low threshold voltage v t - 1.3 1.5 1.7 v v dd = 5 v input high threshold voltage v t+ 3.2 3.5 3.8 v v dd = 5 v hystersis v th 1.5 2 v v dd = 5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v in ts - ttl level schmitt - triggered input pin input low threshold voltage v t - 0.5 0.8 1.1 v v dd = 5 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 5 v hystersis v th 0.5 1.2 v v dd = 5 v input h igh leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v in tsp3 - 3.3 v ttl level schmitt - triggered input pin input low threshold voltage v t - 0.5 0.8 1.1 v v dd = 3.3 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 3.3 v hystersis v th 0.5 1.2 v v dd = 3.3 v input high leakage i lih +10 m a v in = 3.3 v input low leakage i lil - 10 m a v in = 0 v
W83627SF preliminary publication release date: nov . 2000 - 137 - revision 0. 6 0 15. application circuits 15.1 parallel port extension fdd 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 we2/slct wd2/pe mob2/busy dsb2/ack pd7 pd6 pd5 dch2/pd4 rdd2/pd3 step2/slin wp2/pd2 dir2/init trk02/pd1 head2/err idx2/pd0 rwc2/afd stb jp 13a ext fdc dch2 trk02 rdd2 dir2 wp2 mob2 rwc2 dsb2 head2 step2 wd2 we2 idx2 parallel port extension fdd mode connection diagram
W83627SF preliminary publication release date: nov . 2000 - 138 - revision 0. 6 0 15.2 parallel port extensi on 2fdd 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 we2/slct wd2/pe mob2/busy dsb2/ack pd5 dch2/pd4 rdd2/pd3 step2/slin wp2/pd2 dir2/init trk02/pd1 head2/err idx2/pd0 rwc2/afd stb jp 13a ext fdc dch2 trk02 rdd2 dir2 wp2 mob2 rwc2 dsb2 head2 step2 wd2 we2 idx2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 dsa2 moa2 parallel port extension 2fdd connection diagram dsa2/pd7 moa2/pd6 15.3 four fdd mode g1 a1 b1 g2 a2 b2 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 dsa moa dsa dsb moa mob w83977f 74ls139 7407(2) mod moc mob dsc dsd dsb
W83627SF preliminary publication release date: nov . 2000 - 139 - revision 0. 6 0 16. ordering instruction part no. kbc firmware remarks W83627SF - aw amikey - 2 tm W83627SF - pw phoenix multikey/42 tm only support 12mhz kbc clock input 17. how to read the top marking example: the top marking of W83627SF - aw inbond W83627SF-aw 821a2b282012345 ? am. mega. 87-96 1st line: winbond logo 2nd line: the type number: W83627SF - aw 3rd line: the source of kbc f/w -- american megatrends incorporated tm 4th line: the tracking code 821 a 2 c 282 012345 821 : packages made in '9 8 , week 21 a : assembly house id; a means ase, s means spil.... etc. 2 : winbond internal use. b : ic revision; a means version a, b means version b 282012345 : wafer production series lot number
W83627SF preliminary publication release date: nov . 2000 - 140 - revision 0. 6 0 18. package dimensions (128 - pin qfp) l l 1 detail f c e b h d 38 39 d 65 64 h e e 1 128 102 103 1.dimension d & e do not include interlead flash. 2.dimension b does not include dambar protrusion/intrusion 3.controlling dimension : millimeter 4.general appearance spec. should be based on final visual inspection spec. . note: 0.003 0 7 0 0.08 0.063 0.037 0.685 0.031 0.677 0.025 0.669 1.60 0.95 17.40 0.80 17.20 0.65 17.00 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 symbol min nom max max nom min dimension in inch dimension in mm b c d e h d h e l y 0 a a l 1 1 2 e 0.20 0.15 0.006 0.008 7 19.90 20.00 20.10 0.783 0.787 0.791 23.00 23.20 23.40 0.905 0.913 0.921 seating plane see detail f y a a 1 a 2 0.35 0.45 0.014 0.018 headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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